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MPC5645S датащи(PDF) 101 Page - Freescale Semiconductor, Inc

номер детали MPC5645S
подробное описание детали  Qorivva MPC5645S Microcontroller Data Sheet
PDF  146 Pages
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производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC5645S датащи(HTML) 101 Page - Freescale Semiconductor, Inc

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Qorivva MPC5645S Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
101
4.18
AC timing
4.18.1
IEEE 1149.1 interface timing
Figure 16. JTAG Test Clock Input Timing
Table 53. JTAG Interface Timing1
1 These specifications apply to JTAG boundary scan only. JTAG timing specified at V
DD = 3.0 V to 3.6 V, TA = -40 to 105 °C, and
CL = 50 pF with SRC = 0b01.
Num
Symbol
C
Characteristic
Min
Max
Unit
SpecID
1tJCYC
CC2
2 Parameter values guaranteed by design.
D TCK Cycle Time
100
—
ns
A1.1
2tJDC
CC2
D TCK Clock Pulse Width (Measured at VDD/2)
40
60
ns
A1.2
3tTCKRISE
CC2
D TCK Rise and Fall Times (40% – 70%)
—
3
ns
A1.3
4tTMSS, tTDIS
CC2
D TMS, TDI Data Setup Time
5
—
ns
A1.4
5tTMSH, tTDIH
CC2
D TMS, TDI Data Hold Time
25
—
ns
A1.5
6tTDOV
CC2
D TCK Low to TDO Data Valid
—
35
ns
A1.6
7tTDOI
CC2
D TCK Low to TDO Data Invalid
0
—
ns
A1.7
8tTDOHZ
CC2
D TCK Low to TDO High Impedance
—
30
ns
A1.8
9tBSDV
CC2
D TCK Falling Edge to Output Valid
—
35
ns
A1.9
10
tBSDVZ
CC2
D TCK Falling Edge to Output Valid out of High
Impedance
—
50
ns
A1.10
11
tBSDHZ
CC2
D TCK Falling Edge to Output High Impedance
—
50
ns
A1.11
12
tBSDST
CC2
D Boundary Scan Input Valid to TCK Rising Edge
50
—
ns
A1.12
13
tBSDHT
CC2
D TCK Rising Edge to Boundary Scan Input Invalid
50
—
ns
A1.13
TCK
1
2
2
3
3



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