SC667201MMG3 datasheet(100/120 Pages) FREESCALE

100 / 120 page

MPC5642A Microcontroller Data Sheet, Rev. 3.1

100

Freescale Semiconductor

Electrical characteristics

3.17.7

eMIOS timing

3.17.8

DSPI timing

DSPI channel frequency support for the MPC5642A MCU is shown in Table 45. Timing specifications are in Table 46.

Table 44. eMIOS timing1

1 eMIOS timing specified at V

DD = 1.14 V to 1.32 V, VDDEH = 4.75 V to 5.25 V, TA = TL to TH, and CL =50 pF with

SRC = 0b00.

Symbol

Characteristic

Value

Unit

Min

Max

1tMIPW

eMIOS Input Pulse Width

—

tCYC

2tMOPW

eMIOS Output Pulse Width

—

tCYC

Table 45. DSPI channel frequency support

System clock

(MHz)

DSPI Use Mode

Maximum usable

frequency (MHz)

Notes

150

LVDS

37.5

Use sysclock /4 divide ratio

Non-LVDS

18.75

Use sysclock /8 divide ratio

120

LVDS

Use sysclock /3 divide ratio. Gives 33/66 duty cycle. Use DSPI

configuration DBR = 0b1 (double baud rate), BR = 0b0000

(scaler value 2) and PBR = 0b01 (prescaler value 3).

Non-LVDS

Use sysclock /6 divide ratio

LVDS

Use sysclock /2 divide ratio

Non-LVDS

Use sysclock /4 divide ratio

Table 46. DSPI timing1,2

Symbol

Characteristic

Condition

Min.

Max.

Unit

1tSCK

SCK Cycle Time3,4,5

24.4 ns

2.9 ms

—

2tCSC

PCS to SCK Delay6

227

—ns

3tASC

After SCK Delay8

219

—ns

4tSDC

SCK Duty Cycle

(

½tSC)  2(½tSC) + 2

5tA

Slave Access Time (SS active to

SOUT driven)

—25

6tDIS

Slave SOUT Disable Time (SS inactive

to SOUT High-Z or invalid)

—25

7tPCSC

PCSx to PCSS time

410

—ns

8tPASC

PCSS to PCSx time

511

—ns

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