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SC667201MMG3 датащи(PDF) 53 Page - Freescale Semiconductor, Inc |
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SC667201MMG3 датащи(HTML) 53 Page - Freescale Semiconductor, Inc |
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53 / 120 page ![]() MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 53 Pinout and signal description GPIO[12:17] GPIO[75:110] GPIO[113:145] GPIO[179:204] GPIO[206:213] GPIO[219] GPIO[244:245] SIU – GPIO Configurable general purpose I/O pins. Each GPIO input and output is separately controlled by an 8-bit input (GPDI) or output (GPDO) register. Additionally, each GPIO pin is configured using a dedicated SIU_PCR register. The GPIO pins are generally multiplexed with other I/O pin functions. See the following reference manual sections for more information: • “Pad Configuration Registers (SIU_PCR)” • “GPIO Pin Data Output Registers (SIU_GPDO0_3 – SIU_GPDO412_413)” • “GPIO Pin Data Input Registers (SIU_GPDI0_3 – SIU_GPDI_232)” RESET SIU – Reset The RESET pin is an active low input. The RESET pin is asserted by an external device during a power-on or external reset. The internal reset signal asserts only if the RESET pin asserts for 10 clock cycles. Assertion of the RESET pin while the device is in reset causes the reset cycle to start over. The RESET pin has a glitch detector which detects spikes greater than two clock cycles in duration that fall below the switch point of the input buffer logic of the VDDEH input pins. The switch point lies between the maximum VIL and minimum VIH specifications for the VDDEH input pins. RSTCFG SIU – Reset Used to enable or disable the PLLREF and the BOOTCFG[0:1] configuration signals. 0: Get configuration information from BOOTCFG[0:1] and PLLREF 1: Use default configuration of booting from internal flash with crystal clock source Note: For the 176-pin QFP and 208-ball BGA packages RSTCFG is always 0, so PLLREF and BOOTCFG signals are used. RSTOUT SIU – Reset The RSTOUT pin is an active low output that uses a push/pull configuration. The RSTOUT pin is driven to the low state by the MCU for all internal and external reset sources. There is a delay between initiation of the reset and the assertion of the RSTOUT pin. See reference manual section “RSTOUT” for details. Table 5. Signal details (continued) Signal Module or function Description |
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