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SC667201MMG3 датащи(PDF) 23 Page - Freescale Semiconductor, Inc

номер детали SC667201MMG3
подробное описание детали  Qorivva MPC5642A Microcontroller
PDF  120 Pages
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производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
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SC667201MMG3 датащи(HTML) 23 Page - Freescale Semiconductor, Inc

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MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
23
Pinout and signal description
1.5.26
Nexus port controller (NPC)
The NPC block provides real-time Nexus Class3+ development support capabilities for the MPC5642A Power Architecture
technology-based MCU in compliance with the IEEE-ISTO 5001-2010 standard. MDO port widths of 4 pins and 12 pins are
available in all packages.
1.5.27
JTAG controller (JTAGC)
The JTAG controller (JTAGC) block provides the means to test chip functionality and connectivity while remaining transparent
to system logic when not in test mode. Testing is performed via a boundary scan technique, as defined in the IEEE 1149.1-2001
standard. All data input to and output from the JTAGC block is communicated in serial format. The JTAGC block is compliant
with the IEEE 1149.1-2001 standard and supports the following features:
IEEE 1149.1-2001 Test Access Port (TAP) interface 4 pins (TDI, TMS, TCK, and TDO)
A 5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions:
— BYPASS, IDCODE, EXTEST, SAMPLE, SAMPLE/PRELOAD, HIGHZ, CLAMP
A 5-bit instruction register that supports the additional following public instructions:
— ACCESS_AUX_TAP_NPC
— ACCESS_AUX_TAP_ONCE
— ACCESS_AUX_TAP_eTPU
— ACCESS_CENSOR
3 test data registers to support JTAG Boundary Scan mode
— Bypass register
— Boundary scan register
— Device identification register
A TAP controller state machine that controls the operation of the data registers, instruction register and associated
circuitry
Censorship Inhibit Register
— 64-bit Censorship password register
— If the external tool writes a 64-bit password that matches the Serial Boot password stored in the internal flash
shadow row, Censorship is disabled until the next system reset.
1.5.28
Development trigger semaphore (DTS)
MPC5642A devices include a system development feature, the Development Trigger Semaphore (DTS) module, that enables
user software to signal to an external tool—by driving a persistent (affected only by reset or an external tool) signal on an
external device pin—that data is available. The DTS includes a register of semaphores (32-bits) and an identification register.
There are a variety of ways this module can be used, including as a component of an external real-time data acquisition system.
2
Pinout and signal description
This section contains the pinouts for all production packages for the MPC5642A device. For pin signal descriptions, please refer
to Table 3
NOTE
Any pins labeled “NC” are to be left unconnected. Any connection to an external circuit or
voltage may cause unpredictable device behavior or damage.



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