SC667201MMG3 datasheet(22/120 Pages) FREESCALE

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MPC5642A Microcontroller Data Sheet, Rev. 3.1

Freescale Semiconductor

Introduction

•

Zero wait states for each write/read operations to the CRC_CFG and CRC_INP registers at the maximum frequency

1.5.22

Error correction status module (ECSM)

The ECSM provides a myriad of miscellaneous control functions regarding program-visible information about the platform

configuration and revision levels, a reset status register, a software watchdog timer, wakeup control for exiting sleep modes,

and information on platform memory errors reported by error-correcting codes and/or generic access error information for

certain processor cores.

The Error Correction Status Module supports a number of miscellaneous control functions for the platform. The ECSM includes

these features:

•

Registers for capturing information on platform memory errors if error-correcting codes (ECC) are implemented

•

For test purposes, optional registers to specify the generation of double-bit memory errors are enabled on the

MPC5642A.

The sources of the ECC errors are:

•

Flash memory

•SRAM

•

Peripheral RAM (FlexRay, CAN, eTPU2 parameter RAM)

1.5.23

Peripheral bridge (PBRIDGE)

The PBRIDGE implements the following features:

•

Duplicated periphery

•

Master access privilege level per peripheral (per master: read access enable; write access enable)

•

Write buffering for peripherals

•

Checker applied on PBRIDGE output toward periphery

•

Byte endianess swap capability

1.5.24

Calibration bus interface

The calibration bus interface controls data transfer across the crossbar switch to/from memories or peripherals attached to the

VertiCal connector in the calibration address space. The calibration bus interface is only available in the VertiCal Calibration

System.

Features include:

•

3.3 V ± 10% I/O (3.0 V to 3.6 V)

•

Memory controller supports various memory types

•

16-bit data bus, up to 22-bit address bus

•

Pin muxing supports 32-bit muxed bus

•

Selectable drive strength

•

Configurable bus speed modes

•

Bus monitor

•

Configurable wait states

1.5.25

Power management controller (PMC)

The PMC contains circuitry to generate the internal 3.3 V supply and to control the regulation of 1.2 V supply with an external

NPN ballast transistor. It also contains low voltage inhibit (LVI) and power-on reset (POR) circuits for the 1.2 V supply, the

3.3 V supply, the 3.3 V/5 V supply of the closest I/O segment (VDDEH1), and the 5 V supply of the regulators (VDDREG).

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