SC667201MMG3 datasheet(76/120 Pages) FREESCALE

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MPC5642A Microcontroller Data Sheet, Rev. 3.1

Freescale Semiconductor

Electrical characteristics

VILEXT

CC D EXTAL input low voltage

Crystal mode13

—Vxtal

– 0.4

TExternal

reference13,14

0VRC33/2

– 0.4

—

CC T XTAL load capacitance

—

CC C XTAL load capacitance11

4MHz

8MHz

12 MHz

16 MHz

20 MHz

40 MHz

tlpll

CC P PLL lock time11,15

——

200

µs

tdc

CC D Duty cycle of reference

—

fLCK

CC D Frequency LOCK range

—

–6

% fsys

fUL

CC D Frequency un-LOCK range

—

–18

% fsys

fCS

fDS

CC D Modulation depth

Center spread

±0.25

±4.0

% fsys

Down spread

–0.5

–8.0

fMOD

CC D Modulation frequency16

——

100

kHz

1 All values given are initial design targets and subject to change.

2 Considering operation with PLL not bypassed

3 All internal registers retain data at 0 Hz.

4 “Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self clocked

mode.

5 Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside

the fLOR window.

6 f

VCO self clock range is 20–150 MHz. fSCM represents fSYS after PLL output divider (ERFD) of 2 through 16 in

enhanced mode.

7 This value is determined by the crystal manufacturer and board design.

8 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum

fSYS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock

signal. Noise injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency

increase the CJITTER percentage for a given interval.

9 Proper PC board layout procedures must be followed to achieve specifications.

10 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of C

JITTER and

either fCS or fDS (depending on whether center spread or down spread modulation is enabled).

11 This value is determined by the crystal manufacturer and board design. For 4 MHz to 40 MHz crystals specified for

this PLL, load capacitors should not exceed these limits.

12 Proper PC board layout procedures must be followed to achieve specifications.

13 This parameter is guaranteed by design rather than 100% tested.

Table 25. PLLMRFM electrical specifications1

(VDDPLL = 1.08 V to 3.6 V, VSS = VSSPLL = 0 V, TA = TL to TH) (continued)

Symbol

Parameter

Conditions

Value

Unit

Min

Max

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