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HT46R0664 датащи(PDF) 43 Page - Holtek Semiconductor Inc |
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HT46R0664 датащи(HTML) 43 Page - Holtek Semiconductor Inc |
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43 / 92 page ![]() Rev. 1.00 4� ����st 1�� �011 Rev. 1.00 43 ����st 1�� �011 HT46R0664 Enhanced A/D+LCD 8-Bit OTP MCU ● A/D Inputs The device has 12 inputs to the A/D converter. All of these analog inputs are pin-shared with I/O pins. If these pins are to be used as A/D inputs and not as I/O pins then the corresponding PCRn bits in the A/D converter control registers, ANCSR0/ANCSR1, must be properly setup. There are no configuration options associated with the A/D converter. If chosen as I/O pins, then full pull-high resistor configuration options remain, however if used as A/D inputs then any pull-high resistor configuration options associated with these pins will be automatically disconnected. Pin Remapping Configuration The pin remapping function enables the function pins TC0 and TC1 to be located on different port pins. It is important not to confuse the Pin Remapping function with the Pin-shared function, the two functions have no interdependence. The PCFG bit in the CTRL0 register allows the two function pins TC0 and TC1 to be remapped to different port pins. After power up, this bit will be reset to zero, which will define the default port pins to which the two functions will be mapped. Changing this bit will move the functions to other port pins. Examination of the pin names on the package diagrams will reveal that some pin function names are repeated, this indicates a function pin that can be remapped to other port pins. If the pin name is bracketed then this indicates its alternative location. Pin names without brackets indicate its default location which is the condition after Power-on. PCFG Bit Status PCFG Bit 0 1 Pin Mappin� TC1/P�1 TC0/P�� TC0/P�1 TC1/P�� I/O Pin Structures The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared structures does not permit all types to be shown. V DD M U X Wa ke - up Se le ct S yst em W ak e- up R ead Da ta R egi st er D Q CK S D Q CK S Co nt ro l Bi t Da ta B us Wr it e C ont ro l Re gi st er Ch ip R es et Re ad C on tr ol R eg is te r Wr it e Da ta R egi st er Da ta B it I/O p in Q Q PA o nl y We ak Pu ll- up Pu ll -H ig h Re gi st er Se le ct Generic Input/Output Ports |
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