HT46R0664 datasheet(31/92 Pages) HOLTEK

31 / 92 page

Rev. 1.00

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Rev. 1.00

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HT46R0664

Enhanced A/D+LCD 8-Bit OTP MCU

Mode Switching

The device is switched between one mode and another using a combination of the CLKMOD bit in

the CTRL0 register and the HALT instruction. The CLKMOD bit chooses whether the system runs

in either the Normal or Slow Mode by selecting the system clock to be sourced from either a high

or low frequency oscillator. The HALT instruction forces the system into either the Idle or Sleep

Mode, depending upon whether the LXT oscillator is running or not. The HALT instruction operates

independently of the CLKMOD bit condition. When a HALT instruction is executed and the LXT

oscillator is not running, the system enters the Sleep mode, in which case, the following conditions

exist:

● The system oscillator will stop running and the application program will stop at the “HALT”

instruction.

● The Data Memory contents and registers will maintain their present condition.

● The WDT will be cleared and resume counting.

● The I/O ports will maintain their present condition.

● In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,

will be cleared.

Standby Current Considerations

As the main reason for entering the Idle/Sleep Mode is to keep the current consumption of the

MCU to as low a value as possible, perhaps only in the order of several micro-amps, there are

other considerations which must also be taken into account by the circuit designer if the power

consumption is to be minimised. Special attention must be made to the I/O pins on the device. All

high-impedance input pins must be connected to either a fixed high or low level as any floating input

pins could create internal oscillations and result in increased current consumption. Care must also

be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should

be placed in a condition in which minimum current is drawn or connected only to external circuits

that do not draw current, such as other CMOS inputs. If the configuration options have enabled the

Watchdog Timer internal oscillator LIRC then this will continue to run when in the Idle/Sleep Mode

and will thus consume some power. For power sensitive applications it may be therefore preferable

to use the system clock source for the Watchdog Timer. The LXT, if configured for use, will also

consume a limited amount of power, as it continues to run when the device enters the Idle/Sleep

Mode. To keep the LXT power consumption to a minimum level the LXTLP bit in the CTRL4

Wake-up

After the system enters the Idle/Sleep Mode, it can be woken up from one of various sources listed

as follows:

● Power-on Reset

● An external falling edge on PA0 to PA7

● A system interrupt

● A WDT overflow

If the system is woken up by Power-on reset, the device will experience a full system reset, however,

if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although

both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can

be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or

executing the clear Watchdog Timer instructions and is set when executing the “HALT” instruction.

The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program

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