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HT46R0664 датащи(PDF) 35 Page - Holtek Semiconductor Inc |
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HT46R0664 датащи(HTML) 35 Page - Holtek Semiconductor Inc |
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35 / 92 page ![]() Rev. 1.00 34 ����st 1�� �011 Rev. 1.00 35 ����st 1�� �011 HT46R0664 Enhanced A/D+LCD 8-Bit OTP MCU time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer. The first is a WDT reset, which means a certain value except 01010B and 10101B written into the WE4~WE0 bit filed, the second is using the Watchdog Timer software clear instructions and the third is via a HALT instruction. There is only one method of using software instruction to clear the Watchdog Timer. That is to use the single “CLR WDT” instruction to clear the WDT. The maximum time out period is when the 218 division ratio is selected. As an example, with a 32 kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 8 second for the 218 division ratio, and a minimum timeout of 7.8ms for the 28 division ration. “ CLR WDT”Instr�ction 8-sta�e Divider WDT Prescaler WE4~WE0 bits WDTC Re�ister Reset MCU LIRC fS fLIRC fS/�8 8-to-1 MUX CLR WS�~WS0 (fS/�8 ~ fS/�18) WDT Time-o�t (�8/fS ~ �18/fS) Watchdog Timer |
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