HT46R0664 datasheet(47/92 Pages) HOLTEK

47 / 92 page

Rev. 1.00

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Rev. 1.00

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HT46R0664

Enhanced A/D+LCD 8-Bit OTP MCU

control of the respective timer. Setting the bit high allows the counter to run. Clearing the bit stops

the counter. Bits 0~2 of the Timer Control Register determine the division ratio of the input clock

prescaler. The prescaler bit settings have no effect if an external clock source is used. If the timer is

in the event count or pulse width capture mode, the active transition edge level type is selected by

the logic level of bit 3 of the Timer Control Register which is known as TnEG. The T0S1, T0S0,

T1S bits select the internal clock source if used.

CTRL1 Register

Bit

Name

T0S1

T0S0

TB00

TB01

—

R/W

—

POR

—

Bit 7~6

T0S1, T0S0: Prescaler/TMR0 clock source

00: fTP=fSYS

Prescaler clock source is fSYS

TMR0 clock sourced from the output clock of the Prescaler

01: fTP=LXT

Prescaler clock source is LXT.

TMR0 clock sourced from the output clock of the Prescaler

10: fTP=PFD0

Prescaler clock source is PFD0.

TMR0 clock sourced from fSYS.

11: undefined

Note: If PWM0C or PWM1C is enabled, the clock source of the Prescaler is selected

to be either fSYS or PFD0 using the T0S1 bit.

Bit 5~4

TB01, TB00: Time base 0 period selection

00: fS/212

01: fS/213

10: fS/214

11: fS/215

Bit 3~0

Unimplemented, read as “0”

TMR0C Register

Bit

Name

T0M1

T0M0

—

T0ON

T0EG

T0PS�

T0PS1

T0PS0

R/W

—

R/W

POR

—

Bit 7,6

T0M1, T0M0: Timer 0 operation mode selection

00: no mode available

01: event counter mode

10: timer mode

11: pulse width capture mode

Bit 5

Unimplemented, read as “0”

Bit 4

T0ON: Timer/event counter counting enable

0: disable

1: enable

Bit 3

T0EG: Event counter active edge selection

1: count on falling edge

0: count on rising edge

Pulse Width Capture active edge selection

1: start counting on rising edge, stop on falling edge

0: start counting on falling edge, stop on rising edge

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