HT66F13 datasheet(43/173 Pages) HOLTEK

43 / 173 page

Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the

status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer

time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack

Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer. The

first is an external hardware reset, which means a low level on the RES pin, the second is using the

Watchdog Timer software clear instructions and the third is via a HALT instruction.

There are two methods of using software instructions to clear the Watchdog Timer, one of which must

be chosen by configuration option. The first option is to use the single

²CLR WDT² instruction while

the second is to use the two commands

²CLR WDT1² and ²CLR WDT2². For the first option, a simple

execution of

²CLR WDT² will clear the WDT while for the second option, both ²CLR WDT1² and

²CLR WDT2² must both be executed alternately to successfully clear the Watchdog Timer. Note that

for this second option, if

²CLR WDT1² is used to clear the Watchdog Timer, successive executions of

this instruction will have no effect, only the execution of a

²CLR WDT2² instruction will clear the

Watchdog Timer. Similarly after the

²CLR WDT2² instruction has been executed, only a successive

²CLR WDT1² instruction can clear the Watchdog Timer.

The maximum time out period is when the 2

15division ratio is selected. As an example, with a 32kHz

LIRC oscillator as its source clock, this will give a maximum watchdog period of around 1 second for

the 2

15 division ratio, and a minimum timeout of 7.8ms for the 28 division ration. If the f

SYS/4 clock is

used as the Watchdog Timer clock source, it should be noted that when the system enters the SLEEP or

IDLE0 Mode, then the instruction clock is stopped and the Watchdog Timer may lose its protecting

purposes. For systems that operate in noisy environments, using the fSUB clock source is strongly

recommended.

Rev.1.10

February9,2011

HT66F13/HT66F14/HT66F15

EnhancedA/DFlashType MCU

8 - s t a g e D i v i d e r

f S

W D T T i m e - o u t

( 2 8 / f S ~ 2 1 5 / f S )

f S / 2 8

W D T P r e s c a l e r

8 - t o - 1 M U X

C l e a r W D T T y p e

C o n f i g u r a t i o n O p t i o n

C L R W D T 1 F l a g

C L R W D T 2 F l a g

1 o r 2 I n s t r u c t i o n s

C L R

f S U B

W S 2 ~ W S 0

( f S / 2 8 ~ f S / 2 1 5 )

f S Y S / 4

C o n f i g u r a t i o n

O p t i o n

WatchdogTimer

HT66F13 датащи(PDF) 43 Page - Holtek Semiconductor Inc

HT66F13 датащи(HTML) 43 Page - Holtek Semiconductor Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL