HT66F13 datasheet(83/173 Pages) HOLTEK

83 / 173 page

As the name of the mode suggests, after a comparison is made, the TM output pin, will change state.

The TM output pin condition however only changes state when a TnAF interrupt request flag is

generated after a compare match occurs from Comparator A. The TnPF interrupt request flag,

generated from a compare match occurs from Comparator P, will have no effect on the TM output pin.

The way in which the TM output pin changes state are determined by the condition of the TnIO1 and

TnIO0 bits in the TMnC1 register. The TM output pin can be selected using the TnIO1 and TnIO0 bits

to go high, to go low or to toggle from its present condition when a compare match occurs from

Comparator A. The initial condition of the TM output pin, which is setup after the TnON bit changes

from low to high, is setup using the TnOC bit. Note that if the TnIO1 and TnIO0 bits are zero then no

pin change will take place.

Timer/Counter Mode

To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively. The

Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the

same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used.

Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be

used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a

normal I/O pin or other pin-shared function.

Rev. 1.10

February 9, 2011

HT66F13/HT66F14/HT66F15

Enhanced A/D Flash Type MCU

Counter Value

0x3FF

CCRP

CCRA

TnON

TnPAU

TnPOL

CCRP Int.

Flag TnPF

CCRA Int.

Flag TnAF

TM O/P Pin

Time

CCRA=0

CCRA = 0

Counter overflow

CCRA > 0 Counter cleared by CCRA value

Pause

Resume

Stop

Counter Restart

TnCCLR = 1; TnM [1:0] = 00

Output pin set to

initial Level Low

if TnOC=0

Output Toggle with

TnAF flag

Note TnIO [1:0] = 10

Active High Output select

Here TnIO [1:0] = 11

Toggle Output select

Output not affected by

TnAF flag. Remains High

until reset by TnON bit

Output Pin

Reset to Initial value

Output controlled by

other pin-shared function

Output Inverts

when TnPOL is high

TnPF not

generated

No TnAF flag

generated on

CCRA overflow

Output does

not change

Compare Match Output Mode -- TnCCLR = 1

Note:

1. With TnCCLR=1 a Comparator A match will clear the counter

2. The TM output pin is controlled only by the TnAF flag

3. The output pin is reset to its initial state by a TnON bit rising edge

4. A TnPF flag is not generated when TnCCLR=1

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