HT66F13 datasheet(84/173 Pages) HOLTEK

84 / 173 page

PWM Output Mode

To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively. The

PWM function within the TM is useful for applications which require functions such as motor control,

heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty

cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent

DC RMS values.

As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated

waveform is extremely flexible. In the PWM mode, the TnCCLR bit has no effect on the PWM

operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one

other one is used to control the duty cycle. Which register is used to control either frequency or duty

cycle is determined using the TnDPX bit in the TMnC1 register. The PWM waveform frequency and

duty cycle can therefore be controlled by the values in the CCRA and CCRP registers.

An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match

occurs from either Comparator A or Comparator P. The TnOC bit in the TMnC1 register is used to

select the required polarity of the PWM waveform while the two TnIO1 and TnIO0 bits are used to

enable the PWM output or to force the TM output pin to a fixed high or low level. The TnPOL bit is

used to reverse the polarity of the PWM output waveform.

· STM, PWM Mode, Edge-aligned Mode, T0DPX=0

CCRP

001b

010b

011b

100b

101b

110b

111b

000b

Period

128

256

384

512

640

768

896

1024

Duty

CCRA

If fSYS = 16MHz, TM clock source is fSYS/4, CCRP = 100b and CCRA =128,

The STM PWM output frequency = (fSYS/4)/512=fSYS/2048 = 7.8125 kHz, duty = 128/512 = 25%.

If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the

PWM output duty is 100%.

· STM, PWM Mode, Edge-aligned Mode, T0DPX=1

CCRP

001b

010b

011b

100b

101b

110b

111b

000b

Period

CCRA

Duty

128

256

384

512

640

768

896

1024

The PWM output period is determined by the CCRA register value together with the TM clock while

the PWM duty cycle is defined by the CCRP register value.

HT66F13/HT66F14/HT66F15

Enhanced A/D Flash Type MCU

Rev. 1.10

February 9, 2011

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