HT66F13 datasheet(72/173 Pages) HOLTEK

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Compact Type TM Operating Modes

The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode,

PWM Mode or Timer/Counter Mode. The operating mode is selected using the TnM1 and TnM0 bits

in the TMnC1 register.

Compare Match Output Mode

To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be set to 00B respectively. In

this mode once the counter is enabled and running it can be cleared by three methods. These are a

counter overflow, a compare match from Comparator A and a compare match from Comparator P.

When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a

compare match occurs from Comparator P, the other is when the CCRP bits are all zero which allows

the counter to overflow. Here both TnAF and TnPF interrupt request flags for the Comparator A and

Comparator P respectively, will both be generated.

If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare

match occurs from Comparator A. However, here only the TnAF interrupt request flag will be

generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when

TnCCLR is high no TnPF interrupt request flag will be generated. If the CCRA bits are all zero, the

counter will overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here the TnAF

interrupt request flag will not be generated.

As the name of the mode suggests, after a comparison is made, the TM output pin will change state.

The TM output pin condition however only changes state when a TnAF interrupt request flag is

generated after a compare match occurs from Comparator A. The TnPF interrupt request flag,

generated from a compare match occurs from Comparator P, will have no effect on the TM output pin.

The way in which the TM output pin changes state are determined by the condition of the TnIO1 and

TnIO0 bits in the TMnC1 register. The TM output pin can be selected using the TnIO1 and TnIO0 bits

to go high, to go low or to toggle from its present condition when a compare match occurs from

Comparator A. The initial condition of the TM output pin, which is setup after the TnON bit changes

from low to high, is setup using the TnOC bit. Note that if the TnIO1 and TnIO0 bits are zero then no

pin change will take place.

Timer/Counter Mode

To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively. The

Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the

same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used.

Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be

used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a

normal I/O pin or other pin-shared function.

PWM Output Mode

To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively. The

PWM function within the TM is useful for applications which require functions such as motor control,

heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty

cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent

DC RMS values.

As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated

waveform is extremely flexible. In the PWM mode, the TnCCLR bit has no effect on the PWM

operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one

other one is used to control the duty cycle. Which register is used to control either frequency or duty

cycle is determined using the TnDPX bit in the TMnC1 register. The PWM waveform frequency and

duty cycle can therefore be controlled by the values in the CCRA and CCRP registers.

HT66F13/HT66F14/HT66F15

Enhanced A/D Flash Type MCU

Rev. 1.10

February 9, 2011

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