HT66F13 datasheet(78/173 Pages) HOLTEK

78 / 173 page

Standard Type TM Register Description

Overall operation of the Standard TM is controlled using a series of registers. A read only register pair

exists to store the internal counter 10-bit value, while a read/write register pair exists to store the

internal 10-bit CCRA value. The remaining two registers are control registers which setup the different

operating and control modes as well as the three CCRP bits.

STM Register List

- HT66F13/ HT66F14

Name

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

TM1C0

T1PAU

T1CK2

T1CK1

T1CK0

T1ON

T1RP2

T1RP1

T1RP0

TM1C1

T1M1

T1M0

T1IO1

T1IO0

T1OC

T1POL

T1DPX

T1CCLR

TM1DL

TM1DH

¾¾¾¾¾¾

TM1AL

TM1AH

¾¾¾¾¾¾

10-bit Standard TM Register List

TM1C0 Register

Bit

76543210

Name

T1PAU

T1CK2

T1CK1

T1CK0

T1ON

T1RP2

T1RP1

T1RP0

R/W

POR

00000000

Bit 7

T1PAU: TM1 Counter Pause Control

0: run

1: pause

The counter can be paused by setting this bit high. Clearing the bit to zero restores normal

counter operation. When in a Pause condition the TM will remain powered up and continue to

consume power. The counter will retain its residual value when this bit changes from low to high

and resume counting from this value when the bit changes to a low value again.

Bit 6~4

T1CK2~T1CK0: Select TM1 Counter clock

000: f

SYS/4

001: f

SYS

010: f

H/16

011: f

H/64

100: f

TBC

101: undefined

110: TCK1 rising edge clock

111: TCK1 falling edge clock

These three bits are used to select the clock source for the TM. Selecting the Reserved clock

input will effectively disable the internal counter. The external pin clock source can be chosen to

be active on the rising or falling edge. The clock source f

SYS is the system clock, while fH and

TBC are other internal clocks, the details of which can be found in the oscillator section.

Bit 3

T1ON: TM1 Counter On/Off Control

0: Off

1: On

This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to

run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting

and turn off the TM which will reduce its power consumption. When the bit changes state from

low to high the internal counter value will be reset to zero, however when the bit changes from

high to low, the internal counter will retain its residual value until the bit returns high again.

If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial

condition, as specified by the T1OC bit, when the T1ON bit changes from low to high.

HT66F13/HT66F14/HT66F15

Enhanced A/D Flash Type MCU

Rev. 1.10

February 9, 2011

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