HT66F13 datasheet(40/173 Pages) HOLTEK

40 / 173 page

EnteringtheIDLE1Mode

There is only one way for the device to enter the IDLE1 Mode and that is to execute the HALT

instruction in the application program with the IDLEN bit in SMOD register equal to

²1² and the

FSYSON bit in the WDTC register equal to

²1². When this instruction is executed under the conditions

described above, the following will occur:

· The system clock, Time Base clock and fSUB clock will be on and the application program will stop at

the

²HALT² instruction.

· The Data Memory contents and registers will maintain their present condition.

· The WDT will be cleared and resume counting if the WDT is enabled regardless of the WDT clock

source which originates from the fSUB clock or from the system clock.

· The I/O ports will maintain their present conditions.

· In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,

will be cleared.

StandbyCurrentConsiderations

As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the

device to as low a value as possible, perhaps only in the order of several micro-amps except in the

IDLE1 Mode, there are other considerations which must also be taken into account by the circuit

designer if the power consumption is to be minimised. Special attention must be made to the I/O pins

on the device. All high-impedance input pins must be connected to either a fixed high or low level as

any floating input pins could create internal oscillations and result in increased current consumption.

This also applies to devices which have different package types, as there may be unbonbed pins. These

must either be setup as outputs or if setup as inputs must have pull-high resistors connected.

Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs.

These should be placed in a condition in which minimum current is drawn or connected only to

external circuits that do not draw current, such as other CMOS inputs. Also note that additional

standby current will also be required if the LIRC oscillator have been enabled.

In the IDLE1 Mode the system oscillator is on, if the system oscillator is from the high speed system

oscillator, the additional standby current will also be perhaps in the order of several hundred

micro-amps.

Wake-up

After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources

listed as follows:

· An external reset

· An external falling edge on Port A

· A system interrupt

· A WDT overflow

If the system is woken up by an external reset, the device will experience a full system reset, how-

ever, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Al-

though both of these wake-up methods will initiate a reset operation, the actual source of the

wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a sys-

tem power-up or executing the clear Watchdog Timer instructions and is set when executing the

²HALT² instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only re-

sets the Program Counter and Stack Pointer, the other flags remain in their original status.

HT66F13/HT66F14/HT66F15

EnhancedA/DFlashType MCU

Rev.1.10

February9,2011

HT66F13 датащи(PDF) 40 Page - Holtek Semiconductor Inc

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