HT66F13 datasheet(75/173 Pages) HOLTEK

75 / 173 page

An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match

occurs from either Comparator A or Comparator P. The TnOC bit in the TMnC1 register is used to

select the required polarity of the PWM waveform while the two TnIO1 and TnIO0 bits are used to

enable the PWM output or to force the TM output pin to a fixed high or low level. The TnPOL bit is

used to reverse the polarity of the PWM output waveform.

· CTM, PWM Mode, Edge-aligned Mode, T0DPX=0

CCRP

001b

010b

011b

100b

101b

110b

111b

000b

Period

128

256

384

512

640

768

896

1024

Duty

CCRA

If fSYS = 16MHz, TM clock source is fSYS/4, CCRP = 100b and CCRA =128,

The CTM PWM output frequency = (fSYS/4)/512=fSYS/2048 = 7.8125 kHz, duty = 128/512 = 25%.

If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the

PWM output duty is 100%.

· CTM, PWM Mode, Edge-aligned Mode, T0DPX=1

CCRP

001b

010b

011b

100b

101b

110b

111b

000b

Period

CCRA

Duty

128

256

384

512

640

768

896

1024

The PWM output period is determined by the CCRA register value together with the TM clock while

the PWM duty cycle is defined by the CCRP register value.

Rev. 1.10

February 9, 2011

HT66F13/HT66F14/HT66F15

Enhanced A/D Flash Type MCU

Counter Value

CCRP

CCRA

TnON

TnPAU

TnPOL

CCRP Int.

Flag TnPF

CCRA Int.

Flag TnAF

TM O/P Pin

(TnOC=1)

Time

Counter cleared

by CCRP

Pause Resume

Counter Stop if

TnON bit low

Counter Reset when

TnON returns high

TnDPX = 0; TnM [1:0] = 10

PWMDutyCycle

set by CCRA

PWM resumes

operation

Output controlled by

other pin-shared function

Output Inverts

when TnPOL = 1

PWM Period

set by CCRP

TM O/P Pin

(TnOC=0)

PWM Mode -- TnDPX = 0

Note:

1. Here TnDPX=0 -- Counter cleared by CCRP

2. A counter clear sets the PWM Period

3. The internal PWM function continues even when TnIO [1:0] = 00 or 01

4. The TnCCLR bit has no influence on PWM operation

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