AT89LP51 datasheet(57/113 Pages) ATMEL

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3709B–MICRO–12/10

AT89LP51/52 - Preliminary

Special Function Register SCON, while the stop bit is ignored. The baud rate is

programmable to either 1/16 or 1/32 the system frequency.

• Mode 3: 11 bits are transmitted (through TXD) or received (through RXD): a start bit (0),

8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). In fact, Mode 3 is the

same as Mode 2 in all respects except the baud rate, which is variable based on Timer 1 or

Timer 2 in Mode 3.

In all four modes, transmission is initiated by any instruction that uses SBUF as a destination

ated in the other modes by the incoming start bit if REN = 1.

Notes:1. SMOD0 is located at PCON.6.

2. fSYS = system frequency. The baud rate depends on SMOD1 (PCON.7).

Table 14-1.

SCON – Serial Port Control Register

SCON Address = 98H

Reset Value = 0000 0000B

Bit Addressable

SM0/FE

SM1

SM2

REN

TB8

RB8

Bit

(SMOD0 = 0/1)(1)

Symbol

Function

Framing error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid

frames and must be cleared by software. The SMOD0 bit must be set to enable access to the FE bit. FE will be set

regardless of the state of SMOD0.

SM0

Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)

SM1

Serial Port Mode Bit 1

SM2

Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the received

9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address. In Mode 1, if SM2 =

1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a Given or Broadcast Address.

In Mode 0, SM2 determines the idle state of the shift clock such that the clock is the inverse of SM2, i.e. when SM2 = 0

the clock idles high and when SM2 = 1 the clock idles low.

REN

Enables serial reception. Set by software to enable reception. Clear by software to disable reception.

TB8

The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. In Mode 0, setting TB8

enables Timer 1 as the shift clock generator.

RB8

In Modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received. In Mode

0, RB8 is not used.

Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the

other modes, in any serial transmission. Must be cleared by software.

Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the

other modes, in any serial reception (except see SM2). Must be cleared by software.

SM0

SM1

Mode

Description

Baud Rate (Compat.)

(2)

Baud Rate (Fast)

(2)

000

shift register

SYS/3 or fSYS/6 or Timer 1

SYS/2 or fSYS/4 or Timer 1

011

8-bit UART

variable (Timer 1 or Timer 2)

102

9-bit UART

SYS/32 or fSYS/16

113

9-bit UART

variable (Timer 1 or Timer 2)

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