AT89LP51 datasheet(7/113 Pages) ATMEL

7 / 113 page

3709B–MICRO–12/10

AT89LP51/52 - Preliminary

2.1

Block Diagram

Figure 2-1.

AT89LP51/52 Block Diagram

2.2

Comparison to AT89S51/52

The AT89LP51/52 is part of a family of devices with enhanced features that are fully binary com-

patible with the 8051 instruction set. The AT89LP51/52 has two modes of operations,

Compatibility mode and Fast mode. In Compatibility mode the instruction timing, peripheral

behavior, SFR addresses, bit assignments and pin functions are identical to Atmel's existing

AT89S51/52 product. Additional enhancements are transparent to the user and can be used if

desired. Fast mode allows greater performance, but with some differences in behavior. The

major enhancements from the AT89S51/52 are outlined in the following paragraphs and may be

useful to users migrating to the AT89LP51/52 from older devices. A summary of the differences

between Compatibility and Fast modes is given in Table 2-1 on page 9. See also the Application

note “Migrating from AT89S52 to AT89LP52.”

2.2.1

Instruction Execution

In Compatibility mode the AT89LP51/52 CPU uses the six-state machine cycle of the standard

8051 where instruction bytes are fetched every three system clock cycles. Execution times in

this mode are identical to AT89S51/52. For greater performance the user can enable Fast mode

4K/8K Bytes

Flash Code

UART

16-bit Timer 0

16-bit Timer 1

Watchdog

Timer

Configurable

Oscillator

Crystal or

Resonator

256 Bytes

Flash Data

16-bit Timer 2

256 Bytes

RAM

XRAM

Interface

8051 Single Cycle CPU

with 12-cycle Compatibility

POR

BOD

Port 0

Configurable I/O

Port 1

Configurable I/O

Port 2

Configurable I/O

Port 3

Configurable I/O

Port 4

Configurable I/O

RC Auxiliary

Oscillator

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