AT89LP51 datasheet(9/113 Pages) ATMEL

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3709B–MICRO–12/10

AT89LP51/52 - Preliminary

2.2.6

Serial Port

The timer prescaler increases the range of achievable baud rates when using Timer 1 to gener-

ate the baud rate in UART Modes 1 or 3, including an increase in the maximum baud rate

available in Compatibility mode. Additional features include automatic address recognition and

framing error detection.

The shift register mode (Mode 0) has been enhanced with more control of the polarity, phase

and frequency of the clock and full-duplex operation. This allows emulation of master serial

pheriperal (SPI) and two-wire (TWI) interfaces.

2.2.7

I/O Ports

The P0, P1, P2 and P3 I/O ports of the AT89LP51/52 may be configured in four different modes.

The default setting depends on the Tristate-Port User Fuse. When the fuse is set all the I/O ports

revert to input-only (tristated) mode at power-up or reset. When the fuse is not active, ports P1,

P2 and P3 start in quasi-bidirectional mode and P0 starts in open-drain mode. P4 always oper-

ates in quasi-bidirectional mode. P0 can be configured to have internal pull-ups by placing it in

quasi-bidirectional or output modes. This can reduce system cost by removing the need for

external pull-ups on Port 0.

The P4.4–P4.7 pins are additional I/Os that replace the normally dedicated ALE, PSEN, XTAL1

and XTAL2 pins of the AT89S51/52. These pins can be used as additional I/Os depending on

the configuration of the clock and external memory.

2.2.8

Security

The AT89LP51/52 does not support the extenal access pin (EA). Therefore it is not possible to

execute from external program memory in address range 0000H–1FFFH. When the third Lockbit

is enabled (Lock Mode 4) external program execution is disabled for all addresses above

1FFFH. This differs from AT89S51/52 where Lock Mode 4 prevents EA from being sampled low,

but may still allow external execution at addresses outside the 8K internal space.

2.2.9

Programming

The AT89LP51/52 supports a richer command set for In-System Programming (ISP). Existing

AT89S51/52 programmers should be able to program the AT89LP51/52 in byte mode. In page

mode the AT89LP51/52 only supports programming of a half-page of 64 bytes and therefore

requires an extra address byte as compared to AT89S51/52. Furthermore the device signature

is located at addresses 0000H, 0001H and 0003H instead of 0000H, 0100H and 0200H.

Table 2-1.

Compatibility Mode versus Fast Mode Summary

Feature

Compatibility

Fast

Instruction Fetch in System Clocks

Instruction Execution Time in System Clocks

6, 12, 18 or 24

1, 2, 3, 4 or 5

Default System Clock Divisor

Default Timer Prescaler Divisor

Pin Sampling Rate (INT0, INT1, T0, T1, T2, T2EX)

Prescaler Rate

System Clock

Minimum RST input pulse in System Clocks

WDIDLE and DISRTO bit locations

AUXR

WDTCON

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