AT89LP51 datasheet(8/113 Pages) ATMEL

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3709B–MICRO–12/10

AT89LP51/52 - Preliminary

by disabling the Compatibility fuse. In Fast mode the CPU fetches one code byte from memory

every clock cycle instead of every three clock cycles. This greatly increases the throughput of

the CPU. Each standard instruction executes in only 1 to 4 clock cycles. See “Instruction Set

Summary” on page 75 for more details. Any software delay loops or instruction-based timing

operations may need to be retuned to achieve the desired results in Fast mode.

2.2.2

System Clock

By default in Compatibility mode the system clock frequency is divided by 2 from the externally

supplied XTAL1 frequency for compatibility with standard 8051s (12 clocks per machine cycle).

The System Clock Divider can scale the system clock versus the oscillator source (See Section

6.4 on page 30). The divide-by-2 can be disabled to operate in X2 mode (6 clocks per machine

cycle) or the clock may be further divided to reduce the operating frequency. In Fast mode the

clock divider defaults to divide by 1.

The system clock source is selectable between the crystal oscillator, an externally driven clock

and an internal 1.8432 MHz auxiliary oscillator.

2.2.3

Reset

The RST pin of the AT89LP51/52 has selectable polarity using the POL pin (formerly EA). When

POL is high the RST pin is active high with a pull-down resistor and when POL is low the RST

pin is active low with a pull-up resistor. For existing AT89S51/52 sockets where EA is tied to

VDD, replacing AT89S51/52 with AT89LP51/52 will maintain the active high reset. Note that

forcing external execution by tying EA low is not supported.

The AT89LP51/52 includes an on-chip Power-On Reset and Brown-out Detector circuit that

ensures that the device is reset from system power up. In most cases a RC startup circuit is not

required on the RST pin, reducing system cost, and the RST pin may be left unconnected if a

board-level reset is not present.

2.2.4

Timer/Counters

A common prescaler is available to divide the time base for Timer 0, Timer 1, Timer 2 and the

WDT. The TPS

3-0 bits in the CLKREG SFR control the prescaler (Table 6-2 on page 30). In

Compatibility mode TPS

3-0 defaults to 0101B, which causes the timers to count once every

machine cycle. The counting rate can be adjusted linearly from the system clock rate to 1/16 of

the system clock rate by changing TPS

3-0. In Fast mode TPS3-0 defaults to 0000B, or the system

clock rate. TPS does not affect Timer 2 in Clock Out or Baud Generator modes.

In Compatibility mode the sampling of the external Timer/Counter pins: T0, T1, T2 and T2EX;

and the external interrupt pins, INT0 and INT1, is also controlled by the prescaler. In Fast mode

these pins are always sampled at the system clock rate.

Both Timer 0 and Timer 1 can toggle their respective counter pins, T0 and T1, when they over-

flow by setting the output enable bits in TCONB.

The Watchdog Timer includes a 7-bit prescaler for longer timeout periods than the AT89S51/52.

Note that in Fast Mode the WDIDLE and DISRTO bits are located in WDTCON and not in

AUXR.

2.2.5

Interrupt Handling

With the addition of the IPH register, the AT89LP51/52 provides four levels of interrupt priority

for greater flexibility in handling multiple interrupts. Also, Fast mode allows for faster interrupt

response due to the shorter instruction execution times.

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