AT89LP51 datasheet(75/113 Pages) ATMEL

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3709B–MICRO–12/10

AT89LP51/52 - Preliminary

16. Instruction Set Summary

The AT89LP51/52 is fully binary compatible with the 8051 instruction set. In Compatibility mode

the AT89LP51/52 has identical execution time with AT89S51/52 and other standard 8051s. The

difference between the AT89LP51/52 in Fast mode and the standard 8051 is the number of

cycles required to execute an instruction. Fast mode instructions may take 1 to 5 clock cycles to

complete. The execution times of most instructions may be computed using Table 16-1. Note

that for the purposes of this table, a clock cycle is one period of the output of the system clock

divider. For Fast mode the divider defaults to 1, so the clock cycle equals the oscillator period.

For Compatibility mode the divider defaults to 2, so the clock cycle is twice the oscillator period,

or conversely the clock count is half the number of oscillator periods.

Table 16-1.

Instruction Execution Times and Exceptions

(1)

Generic Instruction Types

Fast Mode Cycle Count Formula

Most arithmetic, logical, bit and transfer instructions

# bytes

Branches and Calls

# bytes + 1

Single Byte Indirect (i.e. ADD A, @Ri, etc.)

RET, RETI

MOVC

MOVX

(3)

MUL

DIV

INC DPTR

Arithmetic

Bytes

Clock Cycles

Hex Code

Compatibility

Fast

ADD A, Rn

28-2F

ADD A, direct

ADD A, @Ri

26-27

ADD A, #data

ADDC A, Rn

38-3F

ADDC A, direct

ADDC A, @Ri

36-37

ADDC A, #data

SUBB A, Rn

98-9F

SUBB A, direct

SUBB A, @Ri

96-97

SUBB A, #data

INC Rn

08-0F

INC direct

INC @Ri

06-07

INC A

DEC Rn

18-1F

DEC direct

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