AT89LP51 datasheet(4/113 Pages) ATMEL

4 / 113 page

3709B–MICRO–12/10

AT89LP51/52 - Preliminary

1.5

Pin Description

Table 1-1.

AT89LP51/52 Pin Description

Pin Number

Symbol

Type

Description

TQFP

PLCC

PDIP

VQFN

1761

P1.5

I/O

P1.5: I/O Port 1 bit 5.

MOSI: SPI master-out/slave-in. In UART SPI mode this pin is an output. During In-

System Programming, this pin is an input.

P1.6

I/O

P1.6: I/O Port 1 bit 6.

MISO: SPI master-in/slave-out. In UART SPI mode this pin is an input. During In-

System Programming, this pin is an output.

3P1.7

I/O

P1.7: I/O Port 1 bit 7.

SCK: SPI Clock. In UART SPI mode this pin is an output. During In-System

Programming, this pin is an input.

4109

RST

I/O

RST: External Reset input (Reset polarity depends on POL pin. See “External Reset”

on page 32.). The RST pin can output a pulse when the internal Watchdog reset is

active.

511

105

P3.0

I/O

P3.0: I/O Port 3 bit 0.

RXD: Serial Port Receiver Input.

Not internally connected

713

117

P3.1

I/O

P3.1: I/O Port 3 bit 1.

TXD: Serial Port Transmitter Output.

P3.2

I/O

P3.2: I/O Port 3 bit 2.

INT0: External Interrupt 0 Input or Timer 0 Gate Input.

915

139

P3.3

I/O

P3.3: I/O Port 3 bit 3.

INT1: External Interrupt 1 Input or Timer 1 Gate Input

P3.4

I/O

P3.4: I/O Port 3 bit 4.

T1: Timer/Counter 0 External input or output.

P3.5

I/O

P3.5: I/O Port 3 bit 5.

T1: Timer/Counter 1 External input or output.

P3.6

I/O

P3.6: I/O Port 3 bit 6.

WR: External memory interface Write Strobe (active-low).

P3.7

I/O

P3.7: I/O Port 3 bit 7.

RD: External memory interface Read Strobe (active-low).

P4.7

I/O

P4.7: I/O Port 4 bit 7.

XTAL2: Output from inverting oscillator amplifier. It may be used as a port pin if the

internal RC oscillator or external clock is selected as the clock source.

P4.6

I/O

P4.6: I/O Port 4 bit 6.

XTAL1: Input to the inverting oscillator amplifier and internal clock generation circuits.

It may be used as a port pin if the internal RC oscillator is selected as the clock

source.

GND

Ground

Not internally connected

P2.0

I/O

P2.0: I/O Port 2 bit 0.

A8: External memory interface Address bit 8.

P2.1

I/O

P2.1: I/O Port 2 bit 1.

A9: External memory interface Address bit 9.

P2.1

I/O

P2.2: I/O Port 2 bit 2.

A10: External memory interface Address bit 10.

AT89LP51 датащи(PDF) 4 Page - ATMEL Corporation

AT89LP51 датащи(HTML) 4 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL