ST10F276Z5 datasheet(106/239 Pages) STMICROELECTRONICS

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System reset

ST10F276Z5

106/239

System reset

System reset initializes the MCU in a predefined state. There are six ways to activate a reset

state. The system start-up configuration is different for each case as shown in Table 61.

19.1

Input filter

On RSTIN input pin an on-chip RC filter is implemented. It is sized to filter all the spikes

shorter than 50 ns. On the other side, a valid pulse shall be longer than 500 ns to grant that

ST10 recognizes a reset command. In between 50 ns and 500 ns a pulse can either be

filtered or recognized as valid, depending on the operating conditions and process

variations.

For this reason all minimum durations mentioned in this Chapter for the different kind of

reset events shall be carefully evaluated taking into account of the above requirements.

In particular, for Short Hardware Reset, where only 4 TCL is specified as minimum input

reset pulse duration, the operating frequency is a key factor. Examples:

●

For a CPU clock of 64 MHz, 4 TCL is 31.25 ns, so it would be filtered. In this case the

minimum becomes the one imposed by the filter (that is 500 ns).

●

For a CPU clock of 4 MHz, 4 TCL is 500 ns. In this case the minimum from the formula

is coherent with the limit imposed by the filter.

Table 61.

Reset event definition(1)

See next Section 19.1 for more details on minimum reset pulse duration.

Reset Source

Flag

RPD

Status

Conditions

Power-on reset

PONR

Low

Power-on

Asynchronous Hardware reset

LHWR

Low

(2)

RSTIN pulse should be longer than 500 ns (Filter) and than settling time for configuration of Port0.

Synchronous Long Hardware

reset

High

tRSTIN > (1032 + 12) TCL + max(4 TCL,

500 ns)

Synchronous Short Hardware

reset

SHWR

High

tRSTIN > max(4 TCL, 500 ns)

tRSTIN ≤ (1032 + 12) TCL + max(4 TCL,

500 ns)

Watchdog Timer reset

WDTR

(3)

The RPD status has no influence unless Bidirectional Reset is activated (bit BDRSTEN in SYSCON): RPD

low inhibits the Bidirectional reset on SW and WDT reset events, that is RSTIN is not activated (refer to

Section 19.4, Section 19.5 and Section 19.6).

WDT overflow

Software reset

SWR

SRST instruction execution

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