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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST10F276Z5 датащи(PDF) 52 Page - STMicroelectronics |
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ST10F276Z5 датащи(HTML) 52 Page - STMicroelectronics |
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52 / 239 page  Bootstrap loader ST10F276Z5 52/239 Figure 7. Hardware provisions to activate the BSL 5.2.5 Memory configuration in bootstrap loader mode The configuration (that is, the accessibility) of the device memory areas after reset in Bootstrap Loader mode differs from the standard case. Pin EA is evaluated when BSL mode is selected to enable or to not enable the external bus: ● If EA = 1, the external bus is disabled (BUSACT0 = 0 in BUSCON0 register); ● If EA = 0, the external bus is enabled (BUSACT0 = 1 in BUSCON0 register). Moreover, while in BSL mode, accesses to the internal IFLASH area are partially redirected: ● All code accesses are made from the special Test-Flash seen in the range 00’0000h to 00’01FFFh; ● User IFLASH is only available for read and write accesses (Test-Flash cannot be read or written); ● Write accesses must be made with addresses starting in segment 1 from 01'0000h, regardless of the value of ROMS1 bit in SYSCON register; ● Read accesses are made in segment 0 or in segment 1 depending on the ROMS1 value; ● In BSL mode, by default, ROMS1 = 0, so the first 32 Kbytes of IFlash are mapped in segment 0. Example In default configuration, to program address 0, the user must put the value 01'0000h in the FARL and FARH registers but to verify the content of the address 0 a read to 00'0000h must be performed. RP0L.4 8k Ω max. Circuit 1 P0L.4 P0L.4 Normal boot BSL External signal RP0L.4 8k Ω max. Circuit 2 |
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