ST10F276Z5 datasheet(37/239 Pages) STMICROELECTRONICS

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ST10F276Z5

Internal Flash memory

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4.4.12

XFlash interface control register

This register is used to configure the XFLASH interface behavior on the XBUS. It allows to

set the number of wait states introduced on the XBUS before the internal READY signal is

given to the ST10 bus master.

SEQER

Sequence error

This bit is automatically set when the control registers (FCR1H/L-FCR0H/L, FARH/L,

FDR1H/L-FDR0H/L) are not correctly filled to execute a valid write operation. in this

case no write operation is executed. This bit has to be software reset.

RESER

Resume error

This bit is automatically set when a suspended program or erase operation is not

resumed correctly due to a protocol error. In this case the suspended operation is

aborted. This bit has to be software reset.

WPF

Write protection flag

This bit is automatically set when trying to program or erase in a sector write

protected. In case of multiple sector erase, the not protected sectors are erased, while

the protected sectors are not erased and bit WPF is set. This bit has to be software

reset.

Table 18.

Flash error register (continued)

Bit

Function

XFICR (0xE E000h)

XBUS

Reset value: 000Fh

987

65432

reserved

WS3

WS2

WS1

WS0

Table 19.

XFlash interface control register

Bit

Function

WS(3:0)

Wait state setting

These three bits are the binary coding of the number of wait states introduced by the

XFLASH interface through the XBUS internal READY signal. Default value after reset

is 1111, that is the up to 15 wait states are set. The following recommendations for the

ST10F276Z5 are hereafter reported:

For fCPU > 40 MHz1 Wait-StateWS(3:0) = ‘0001’

For fCPU ≤ 40 MHz0 Wait-StateWS(3:0) = ‘0000’

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