ST10F276Z5 datasheet(82/239 Pages) STMICROELECTRONICS

82 / 239 page

Interrupt system

ST10F276Z5

82/239

8.2

Exception and error traps list

Table 43 shows all of the possible exceptions or error conditions that can arise during run-

time.

ASC1 Error

PLL Unlock / OWD

PWM1 Channel 3...0

Table 42.

X-Interrupt detailed mapping (continued)

XP0INT

XP1INT

XP2INT

XP3INT

Table 43.

Trap priorities

Exception Condition

Trap

Flag

Trap

Vector

Location

Trap

Number

Trap*

Priority

Reset Functions(1):

Hardware Reset

Software Reset

Watchdog Timer Overflow

The resets have the highest priority level and the same trap number.

The PSW.ILVL CPU priority is forced to the highest level (15) when these exceptions are serviced.

RESET

00’0000h

00h

III

Class A Hardware Traps(2):

Non-Maskable Interrupt

Stack Overflow

Stack Underflow

Each class A traps has a dedicated trap number (and vector). They are prioritized in the second priority

level.

NMI

STKOF

STKUF

NMITRAP

STOTRAP

STUTRAP

00’0008h

00’0010h

00’0018h

02h

04h

06h

Class B Hardware Traps(3):

Undefined Opcode

MAC Interruption

Protected Instruction Fault

Illegal word Operand Access

Illegal Instruction Access

Illegal External Bus Access

All the class B traps have the same trap number (and vector) and the same lower priority compare to the

class A traps and to the resets.

UNDOPC

MACTRP

PRTFLT

ILLOPA

ILLINA

ILLBUS

BTRAP

00’0028h

0Ah

Reserved

[002Ch - 003Ch]

[0Bh - 0Fh]

Software Traps

TRAP Instruction

Any

0000h – 01FCh

in steps of 4h

Any

[00h - 7Fh]

Current

CPU

Priority

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