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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST10F276Z5 датащи(PDF) 25 Page - STMicroelectronics |
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ST10F276Z5 датащи(HTML) 25 Page - STMicroelectronics |
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25 / 239 page  ST10F276Z5 Internal Flash memory 25/239 4 Internal Flash memory 4.1 Overview The on-chip Flash is composed by two matrix modules each one containing one array divided in two banks that can be read and modified independently one of the other: one bank can be read while another bank is under modification. Figure 4. Flash modules structure The write operations of the 4 banks are managed by an embedded Flash program/erase controller (FPEC). The high voltages needed for program/erase operations are internally generated. The data bus is 32-bit wide. Due to ST10 core architecture limitation, only the first 512 Kbytes are accessed at 32-bit (internal Flash bus, see I-BUS), while the remaining 320 Kbytes are accessed at 16-bit (see X-BUS). 4.2 Functional description 4.2.1 Structure The following table shows the address space reserved to the Flash module. Bank 1: 128 Kbyte Bank 0: 384 Kbyte program memory HV and Ref. generator Program/erase controller I-BUS interface + 8 Kbyte test-Flash Bank 3: 128 Kbyte Bank 2: 192 Kbyte program memory XFLASH (Module X) X-BUS interface IFLASH (Module I) Control section program memory program memory Table 3. Flash modules absolute mapping Description Addresses Size IFLASH sectors 0x00 0000 to 0x08 FFFF 512 Kbyte XFLASH sectors 0x09 0000 to 0x0D FFFF 320 Kbyte Registers and Flash internal reserved area 0x0E 0000 to 0x0E FFFF 64 Kbyte |
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