IXP45X datasheet(128/148 Pages) INTEL

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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—Datasheet

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

Datasheet

August 2006

128

Document Number: 306261-004US

Table 67.

Intel Simplex Mode Values

Symbol

Parameter

Min.

Max.

Units

Notes

Taddr2valcs

Valid address to valid chip select

Cycles

1, 2, 7

Tdval2valwrt

Write data valid prior to EXPB_IO_WRITE_N falling edge

Cycles

3, 7

Twrpulse

Pulse width of the EXP_IO_WRITE_N

Cycles

4, 7

Tdholdafterwr

Valid data after the rising edge of EXPB_IO_WRITE_N

Cycles

5, 7

Trdsetup

Data valid required before the rising edge of

EXP_IO_READ_N

14.7

Trdhold

Data hold required after the rising edge of

EXP_IO_READ_N

2ns

Trecov

Time required between successive accesses on the

expansion interface.

116

Cycles

Notes:

EX_ALE is not valid in simplex mode of operation.

Setting the address phase parameter (T1) will adjust the duration that the address appears to the

external device.

Setting the data setup phase parameter (T2) will adjust the duration that the data appears prior to a

data strobe (read or write) to an external device.

Setting the data strobe phase parameter (T3) will adjust the duration that the data strobe appears

(read or write) to an external device. Data will be available during this time as well.

Setting the data hold strobe phase parameter (T4) will adjust the duration that the chip selects,

address, and data (during a write) will be held.

Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on

the expansion interface.

T is the period of the clock measured in ns.

Clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in

synchronous mode.

Timing was designed for a system load between 5pF and 60pF for high drive setting

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