IXP45X datasheet(124/148 Pages) INTEL

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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—Datasheet

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

Datasheet

August 2006

124

Document Number: 306261-004US

ADDR/CTRL output hold time after the rising

edge of the DDRI_M_CLK. Address and control

signals consist of DDRI_RAS_N, DDRI_CAS_N,

DDRI_CS_N, DDRI_WE_N, DDRI_BA, DDRI_MA,

and DDRI_CKE.

2.3

Output valid for DDRI_DQ, DDRI_CB, and

DDRI_DM prior to each edge of DDRI_DQS.

1.0

DDRI_DQ, DDRI_CB, and DDRI_DM output hold

time after each edge of the DDRI_DQS.

1.0

Figure 30.

DDRI SDRAM Read Timings (2.0 CAS Latency)

Figure 31.

DDRI SDRAM Read Timings (2.5 CAS Latency)

Table 63.

DDRI SDRAM Write Timings Values (Sheet 2 of 2)

Symbol

Parameter

Min.

Max.

Units

Notes

Notes:

DDRI_M_CLK is representative of all DDRI_CK and DDRI_CK_N signals. The rising edge of

DDRI_M_CLK represents the crossover point of the respective DDRI_CK and DDRI_CK_N signals.

The skew between the separate DDR clocks have been compensated in the timings which have been

described. The period to period clock jitter on each DDRI_M_CLK pair is spec’ed at +/-100ps.

DDRI_M_CLK

DDRI_DQS

DDRI_RCVENOUT_N

DDRI_RCVENIN_N

DDRI_DQ, _CB, _DM

RD CMD

DDRI_M_CLK

DDRI_DQS

DDRI_RCVENOUT_N

DDRI_RCVENIN_N

DDRI_DQ, _CB, _DM

RDCMD

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