IXP45X datasheet(132/148 Pages) INTEL

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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—Datasheet

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

Datasheet

August 2006

132

Document Number: 306261-004US

Table 70.

HPI* Timing Symbol Description

State

Description

Min

Max

Unit

Notes

Address Timing

Cycles

1, 5, 6

Setup/Chip Select Timing

Cycles

2, 6

Strobe Timing

Cycles

3, 5, 6

Hold Timing

Cycles

Recovery Phase

Cycles

Table 71.

HPI*–8 Mode Write Accesses Values

Symbol

Parameter

Min.

Max.

Units

Notes

Tadd_setup

Valid time that address is asserted on the line. The

address is asserted at the same time as chip select.

Cycles

1, 5, 6

Tcs2hds1val

Delay from chip select being active and the HDS1 data

strobe being active.

Cycles

5, 6

Thds1_pulse

Pulse width of the HDS1 data strobe

Cycles

2, 4, 5

Tdata_setup

Data valid prior to the rising edge of the HDS1 data

strobe.

Cycles

3, 5, 6

Tdata_hold

Data valid after the rising edge of the HDS1 data strobe.

Cycles

3, 6

Trecov

Time required between successive accesses on the

expansion interface.

217

Cycles

4, 6

Notes:

The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T

clocks for the address phase. This setting is required to ensure that in the event of an HRDY, the

IXP45X/IXP46X network processors have had sufficient time to recognize the HRDY and hold the

address phase for at least one clock pulse after the HRDY is de-active.

The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three

T clocks for setup phase.

The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T

clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the

IXP45X/IXP46X network processors have had sufficient time to recognize the HRDY and hold the

data setup phase for at least one clock pulse after the HRDY is de-active

Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on

the Expansion Bus interface.

HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1

or T3 until HRDY is de-active

One cycle is the period of the Expansion Bus clock.

Timing was designed for a system load between 5 pF and 60 pF for high drive setting.

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