IXP45X datasheet(125/148 Pages) INTEL

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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

August 2006

Datasheet

Document Number: 306261-004US

125

Datasheet—Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

5.6.2.7

Expansion Bus

5.6.2.7.1

Expansion Bus Synchronous Operation

Table 64.

DDRI SDRAM Read Timing Values

Symbol

Parameter

Min.

Max.

Units

Notes

DDRI_RCVENOUT_N minimum output valid time

after DDRI_M_CLK

0.9

DDRI_RCVENOUT_N maximum output valid

time after DDRI_M_CLK

2.7

DDRI_RCVENIN_N input valid time before

DDRI_DQS

3.6

DDRI_RCVENIN_N hold time from DDRI_DQS

valid

-0.1

Maximum delay for Data valid after any edge of

DDRI_DQS. Both of these signal are inputs from

the memory during read operations.

0.75

Maximum guaranteed time before data begins

to transition to the next valid data prior to any

DDRI_DQS clock edge. Both of these signal are

inputs from the memory during read operations.

This time in conjunction with timing parameter

T5 specify the window for which the DDRI data

signals can operate with the memory controller

on the IXP45X/IXP46X network processors.

1.0

Notes:

It is recommended that IBIS models be used to verify signal integrity on individual designs

Figure 32.

Expansion Bus Synchronous Timing

EX_CLK

EX_DATA, _BE_N, PARITY -

output_signals

EX_ control signals -

output_signals

EX_DATA, _BE_N, PARITY -

input_signals

EX_ control signals -

input_signals

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