IXP45X datasheet(127/148 Pages) INTEL

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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

August 2006

Datasheet

Document Number: 306261-004US

127

Datasheet—Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

Table 66.

Intel Multiplexed Mode Values

Symbol

Parameter

Min.

Max.

Units

Notes

Talepulse

Pulse width of ALE (ADDR is valid at the rising edge of ALE)

Cycles 1, 7

Tale2addrhold

Valid address hold time after from falling edge of ALE

Cycles 1, 2, 7

Tdval2valwrt

Write data valid prior to WR_N falling edge

Cycles 3, 7

Twrpulse

Pulse width of the WR_N

Cycles 4, 7

Tdholdafterwr

Valid data after the rising edge of WR_N

Cycles 5, 7

Tale2valcs

Valid chip select after the falling edge of ALE

Cycles 7

Trdsetup

Data valid required before the rising edge of RD_N

14.7

Trdhold

Data hold required after the rising edge of RD_N

Trecov

Time needed between successive accesses on expansion

interface.

116

Cycles 6

Notes:

The EX_ALE signal is extended form T to 4T nnsec based on the programming of the T1 timing

parameter. The parameter Tale2addrhold is fixed at T.

Setting the address phase parameter (T1) will adjust the duration that the address appears to the

external device.

Setting the data setup phase parameter (T2) will adjust the duration that the data appears prior to a

data strobe (read or write) to an external device.

Setting the data strobe phase parameter (T3) will adjust the duration that the data strobe appears

(read or write) to an external device. Data will be available during this time as well.

Setting the data hold strobe phase parameter (T4) will adjust the duration that the chip selects,

address, and data (during a write) will be held.

Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the

expansion interface.

T is the period of the clock measured in ns.

Clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in

synchronous mode.

Timing was designed for a system load between 5pF and 60pF for high drive setting

Figure 34.

Intel Simplex Mode

A9586-01

EX_CLK

EX_ADDR

EX_DATA

EX_RD_N

EX_DATA

EX_WR_N

Valid Address

Output Data

1-16 Cycles

1-4 Cycles

EX_CS_N

Twrpulse

Trecov

Taddr2valcs

Tdval2valwrt

Input Data

Tdhold2afterwr

1-16 Cycles

1-4 Cycles

Trdsetup

Trdhold

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