IXP45X datasheet(123/148 Pages) INTEL

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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

August 2006

Datasheet

Document Number: 306261-004US

123

Datasheet—Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

5.6.2.6

DDRI SDRAM Bus

Table 62.

MDIO Timings Values

Symbol

Parameter

Min.

Max.

Units

Notes

ETH_MDIO, clock to output timing with respect to

rising edge of ETH_MDC clock

ETH_MDC/2

+ 15 ns

ETH_MDIO output hold timing after the rising

edge of ETH_MDC clock

ETH_MDIO input setup prior to rising edge of

ETH_MDC clock

ETH_MDIO hold time after the rising edge of

ETH_MDC clock

ETH_MDC clock period

125

500

Note:

Timing was designed for a system load between 5pF and 20pF

Figure 29.

DDRI SDRAM Write Timings

Table 63.

DDRI SDRAM Write Timings Values (Sheet 1 of 2)

Symbol

Parameter

Min.

Max.

Units

Notes

Output valid for DDRI_DQS prior to each edge of

DDRI_M_CLK.

1.4

DDRI_DQS output hold time after each edge of

the DDRI_M_CLK.

1.0

Output valid for ADDR/CTRL prior to the rising

edge of DDRI_M_CLK. Address and control

signals consist of DDRI_RAS_N, DDRI_CAS_N,

DDRI_CS_N, DDRI_WE_N, DDRI_BA, DDRI_MA,

and DDRI_CKE.

2.5

Notes:

DDRI_M_CLK is representative of all DDRI_CK and DDRI_CK_N signals. The rising edge of

DDRI_M_CLK represents the crossover point of the respective DDRI_CK and DDRI_CK_N signals.

The skew between the separate DDR clocks have been compensated in the timings which have been

described. The period to period clock jitter on each DDRI_M_CLK pair is spec’ed at +/-100ps.

DDRI_M_CLK

ADDR/CTRL

DDRI_DQS

DDRI_DQ, _CB, _DM

ADDR/CMDVALID

DATAVALID

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