PCF2123TS datasheet(33/55 Pages) NXP

33 / 55 page

PCF2123_2

Product data sheet

Rev. 02 — 4 December 2009

33 of 55

NXP Semiconductors

PCF2123

SPI Real time clock/calendar

The transmission is controlled by the active HIGH chip enable signal CE. The ﬁrst byte

transmitted is the command byte. Subsequent bytes will be either data to be written or

data to be read. Data is sampled on the rising edge of the clock and transferred internally

on the falling edge.

The command byte deﬁnes the address of the ﬁrst register to be accessed and the

read/write mode. The address counter will auto increment after every access and will

rollover to zero after the last register is accessed. The read/write bit (R/W) deﬁnes if the

following bytes will be read or write information.

In Figure 25, the register Seconds is set to 45 seconds and the register Minutes is set to

10 minutes.

Table 41.

Serial interface

Symbol

Function

Description

chip enable input

when LOW, the interface is reset; pull-down resistor included;

active input may be higher than VDD, but may not be wired

permanently HIGH

SCL

serial clock input

when CE is LOW, this input may ﬂoat; input may be higher

than VDD

SDI

serial data input

when CE is LOW, input may ﬂoat; input may be higher than

VDD; input data is sampled on the rising edge of SCL

SDO

serial data output

push-pull output; drives from VSS to VDD; output data is

changed on the falling edge of SCL; will be high-Z when not

driving; may be connected directly to SDI

Fig 23. SDI, SDO conﬁgurations

Fig 24. Data transfer overview

Table 42.

Command byte deﬁnition

Bit

Symbol

Value

Description

7R/W

data read or data write selection

write data

read data

6 to 4 SA

001

subaddress; other codes will cause the device to ignore

data transfer

3 to 0

0h to Fh

001aai560

SDI

two wire mode

SDO

SDI

single wire mode

SDO

001aaf914

COMMAND

data bus

chip enable

DATA

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