PCF2123TS datasheet(23/55 Pages) NXP

23 / 55 page

PCF2123_2

Product data sheet

Rev. 02 — 4 December 2009

23 of 55

NXP Semiconductors

PCF2123

SPI Real time clock/calendar

When reading the timer, the current countdown value is returned and not the initial

value n. Since it is not possible to freeze the countdown timer counter during read back, it

is recommended to read the register twice and check for consistent results.

Timer source clock frequency selection of 1 Hz and 1

⁄

60 Hz will be affected by the

Offset_register. The duration of a program period will vary according to when the offset is

initiated. For example, if a 100 s timer is set using the 1 Hz clock as source, then some

100 s periods will contain correction pulses and therefor be longer or shorter depending

on the setting of the Offset_register. See Section 9.11 to understand the operation of the

Offset_register.

9.8.5 Timer ﬂags

When a minute or second interrupt occurs, bit MSF is set logic 1. Similarly, at the end of a

timer countdown or alarm event, bit TF or AF are set logic 1. These bits maintain their

value until overwritten by software. If both countdown timer and minute or second

interrupts are required in the application, the source of the interrupt can be determined by

reading these bits. To prevent one ﬂag being overwritten while clearing another a logical

AND is performed during a write access. A ﬂag is cleared by writing logic 0 whilst a ﬂag is

not cleared by writing logic 1. Writing logic 1 will result in the ﬂag value remaining

unchanged.

Three examples are given for clearing the ﬂags. Clearing the ﬂags is made by a write

command, therefore bits 7, 6, 4, 1 and 0 must be written with their previous values.

Repeatedly re-writing these bits has no inﬂuence on the functional behavior.

Table 31, Table 32 and Table 33 show what instruction must be sent to clear the

appropriate ﬂag.

Clearing the alarm ﬂag (bit AF) operates in exactly the same way, see Section 9.7.5.

Table 30.

Flag location in register Control_2

Bit

Control_2

MSF

Table 31.

Example to clear only TF (bit 2) in register Control_2

Bit

Control_2

Table 32.

Example to clear only MSF (bit 5) in register Control_2

Bit

Control_2

Table 33.

Example to clear both TF and MSF (bit 2 and bit 5) in register Control_2

Bit

Control_2

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