ADS5400IPZP datasheet(15/48 Pages) TI

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ADS5400

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SLAS611B – OCT 2009 – REVISED MARCH 2010

Table 2. PIN FUNCTIONS

DESCRIPTION

NAME

NO.

AINP, AINN

94, 95

Analog differential input signal (positive, negative). Includes 100-

Ω differential load on-chip.

1, 76, 86, 90, 92,

AVDD5

Analog power supply (5 V)

97, 99

AVDD3

2, 7, 9, 85

Analog power supply (3.3 V)

DVDD3

24, 38, 50, 64

Output driver power supply (3.3 V)

3, 6, 8, 84, 88, 91,

AGND

Analog Ground

93, 96, 98, 100

DGND

25, 39, 51, 65

Digital Ground

CLKINP,

4, 5

Differential input clock (positive, negative). Includes 160-

Ω differential load on-chip.

CLKINN

DA0N, DA0P

46, 47

Bus A, LVDS digital output pair, least-significant bit (LSB) (P = positive output, N = negative output)

DA1N–DA10N, 48-49, 52-59, 62-63,

Bus A, LVDS digital output pairs (bits 1- 10)

DA1P-DA10P

66-73

DA11N,

74, 75

Bus A, LVDS digital output pair, most-significant bit (MSB)

DA11P

CLKOUTAN,

60, 61

Bus A, Clock Output (Data ready), LVDS output pair

CLKOUTAP

DB0N, DB0P

40, 41

Bus B, LVDS digital output pair, least-significant bit (LSB) (P = positive output, N = negative output)

DB1N–DB10N,

14-23, 28-37

Bus B, LVDS digital output pairs (bits 1- 10)

DB1P-DB10P

DB11N,

12, 13

Bus B, LVDS digital output pair, most-significant bit (MSB)

DB11P

CLKOUTBN,

26, 27

Bus B, Clock Output (Data ready), LVDS output pair

CLKOUTBP

OVRAN,

Bus A, Overrange indicator LVDS output. A logic high signals an analog input in excess of the

44, 45

OVRAP

full-scale range. Becomes SYNCOUTA when SYNC mode is enabled in register 0x05.

OVRBN,

Bus B, Overrange indicator LVDS output. A logic high signals an analog input in excess of the

42, 43

OVRBP

full-scale range. Becomes SYNCOUTB when SYNC mode is enabled in register 0x05.

Digital Reset Input, LVDS input pair. Inactive if logic low. When clocked in a high state, this is used

RESETN,

for resetting the polarity of CLKOUT signal pair(s). If SYNC mode is enabled in register 0x05, this

10, 11

RESETP

input also provides a SYNC time-stamp with the data sample present when RESET is clocked by

the ADC, as well as CLKOUT polarity reset. Includes 100-

Ω differential load on-chip.

SCLK

Serial interface clock.

Bi-directional serial interface data in 3-pin mode (default) for programming/reading internal registers.

SDIO

In 4-pin interface mode (reg 0x01), the SDIO pin is an input only.

Uni-directional serial interface data in 4-pin mode (reg 0x01) provides internal register settings. The

SDO

SDO pin is in high-impedance state in 3-pin interface mode (default).

Active low serial data enable, always an input. Use to enable the serial interface. Internal 100k

SDENB

pull-up resistor.

Reference voltage input (2V nominal). A 0.1mF capacitor to AGND is recommended, but not

VREF

required.

Enable single output bus mode (2-bus mode is default), active high. This pin is logic OR'd with addr

ENA1BUS

81(1)

0x02h bit<0>.

Enable Powerdown, active high. Places the converter into power-saving sleep mode when high. This

ENPWD

82(1)

pin is logic OR'd with addr 0x05h bit<6>.

Enable External Reference Mode, active high. Device uses an external voltage reference when high.

ENEXTREF

83(1)

This pin is logic OR'd with addr 0x05h bit<2>.

Analog input common mode voltage, Output (for DC-coupled applications, nominally 2.5V). A 0.1mF

VCM

capacitor to AGND is recommended, but not required.

(1)

This pin contains an internal ~40k

Ω pull-down resistor, to ground.

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