ADS5400IPZP datasheet(35/48 Pages) TI

35 / 48 page

Clock Common Mode − V

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

G016

fS = 1 GSPS

fIN = 1498.5 MHz

fIN = 601.13 MHz

fIN = 100.33 MHz

fIN = 901.13 MHz

Clock Common Mode − V

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

G017

fS = 1 GSPS

fIN = 1498.5 MHz

fIN = 901.13 MHz

fIN = 100.33 MHz

fIN = 601.13 MHz

SNR(dBc)=-20xLOG10(2x

)

TOTAL

=(j

)

TOTAL

ADC

CLOCK

1/2

ADS5400

www.ti.com

SLAS611B – OCT 2009 – REVISED MARCH 2010

Figure 35. ADS5400 SFDR vs Clock Common Mode

Figure 36. ADS5400 SNR vs Clock Common Mode

To understand how to determine the required clock jitter, an example is useful. The ADS5400 is capable of

achieving 58.7 dBFS SNR at 850 MHz of analog input frequency. To achieve SNR at 850 MHz, the external

clock source rms jitter must be at least 210fs when combined with the 125fs of internal aperture jitter in order for

the total rms jitter to be 244fs. A summary of maximum recommended rms clock jitter as a function of analog

input frequency is provided in Table 18 (using 125fs of internal aperture jitter). The equations used to create the

table are also presented.

Table 18. Recommended RMS Clock Jitter

INPUT FREQUENCY

MEASURED SNR

TOTAL JITTER

MAXIMUM EXT CLOCK JITTER

(MHz)

(dBc)

(fs rms)

125

58.1

1585

1580

600

57.8

318

342

850

57.7

244

210

1200

56.6

196

151

1700

54.7

172

119

Equation 1 and Equation 2 are used to estimate the required clock source jitter.

(1)

(2)

where:

jTOTAL = the rms summation of the clock and ADC aperture jitter;

jADC = the ADC internal aperture jitter which is located in the data sheet;

jCLOCK = the rms jitter of the clock at the clock input pins to the ADC; and

fIN = the analog input frequency.

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