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SLAS611B – OCT 2009 – REVISED MARCH 2010

TIMING CHARACTERISTICS

(1)

(continued)

noted)

PARAMETER

TEST CONDITIONS/NOTES

MIN

TYP

MAX

UNIT

(3)

Setup time, single bus mode

Data valid to CLKOUT edge, 50% CLKIN duty cycle

290p

s

185p

CLKOUT edge to Data invalid, 50% CLKIN duty

Hold time, single bus mode

410p

s

cycle

65p

Setup time, dual bus mode

Data valid to CLKOUT edge, 50% CLKIN duty cycle

550p

s

CLKOUT edge to Data invalid, 50% CLKIN duty

Hold time, dual bus mode

1150p

s

cycle

LVDS rise time

400

ps

Mmeasured 20% to 80%

LVDS output fall time

400

ps

LVDS INPUT TIMING (RESETIN)

RESET setup time

RESETP going HIGH to CLKINP going LOW

300

ps

RESET hold time

CLKINP going LOW to RESETP going LOW

300

ps

RESET input capacitance

Differential

1

pF

RESET input current

±1

µA

SERIAL INTERFACE TIMING

Setup time, serial enable

SDENB falling to SCLK rising

20

ns

Hold time, serial enable

SCLK falling to SENDB rising

25

ns

Setup time, SDIO

SDIO valid to SCLK rising

10

ns

Hold time, SDIO

SCLK rising to SDIO transition

10

ns

Frequency

10

MHz

SCLK period

100

ns

Minimum SCLK high time

40

ns

Minimum SCLK low time

40

ns

Rise time

10pF

10

ns

Fall time

10pF

10

ns

Data output (SDO/SDIO) delay after SCLK falling,

Data output delay

75

ns

10pF load

(3)

In single bus mode at 1GSPS (1ns clock), the minimum output setup/hold times over process and temperature provide a minimum

700ps of data valid window, with 300ps of uncertainity.

Copyright © 2009–2010, Texas Instruments Incorporated

7

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