ADS5400IPZP datasheet(38/48 Pages) TI

38 / 48 page

ADS5400

SLAS611B – OCT 2009 – REVISED MARCH 2010

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Test Patterns

Determining the closure of timing or validating the digital interface can be difficult in normal operation. Therefore,

test patterns are available in register 0x06. One pattern toggles the outputs between all 1s and all 0s. Another

pattern generates a 7-bit PRBS (pseudo-random bit sequence).

In dual bus mode, the toggle mode could be in the same phase on bus A and B (bus A and B outputting 1s or 0s

together), or could be out of phase (bus A outputting 1s while bus B outputs 0s). The start phase cannot be

controlled.

The PRBS output sequence is a standard 27-1 pseudo-random sequence generated by a feedback shift register

where the two last bits of the shift register are exclusive-OR’ed and fed back to the first bit of the shift register.

The standard notation for the polynomial is x7 + x6 + 1. The PRBS generator is not reset, so there is no initial

position in the sequence. The pattern may start at any position in the repeating 127-bit long pattern and the

pattern repeats as long as the PRBS mode is enabled. The data pattern from the PRBS generator is used for all

of the LVDS parallel outputs, so when the pattern is ‘1’ then all of the LVDS outputs are outputting ‘1’ and when

the pattern is ‘0’ then all of the LVDS drivers output ‘0’. To determine if the digital interface is operating properly

with the PRBS sequence, the user must generate the same sequence in the receiving device, and do a

shift-and-compare until a matching sequence is confirmed.

Die Identification and Revision

A unique 64-bit die indentifier code can be read from registers 0x17 through 0x1E. An 8-bit die revision code is

available in register 0x1F.

Die Temperature Sensor

In register 0x05, the die temperature sensor can be enabled. The sensor is power controlled independently of

global powerdown, so that it and the SPI can be used to monitor the die temperature even when the remainder

of the ADC is in sleep mode. Register 0x08 is used to read values which can be mapped to the die temperature.

The exact mapping is detailed in the register map. Care should be taken not to exceed a maximum die

temperature of 150°C for prolonged periods of time in order to maintain the life of the device.

Interleaving

Gain Adjustment

A signal gain adjustment is available in registers 0x00 and 0x01. The allowable fullscale range for the ADC is

1.52 - 2VPP and can be set with 12-bit adjustment resolution across this range. For equal up/down gain

adjustment of the system and ADC gain mismatches, a nominal starting point of 1.75VPP could be programmed,

in which case ±250mV of adjustment range would be provided.

Offset Adjustment

Analog offset adjustment is available in register 0x03 and 0x04. This provides ±30mV of adjustment range with

9-bit adjustment resolution of 120uV per step. At production test, the default code for this register setting is set to

a value that provides 0mV of ADC offset. For optimum spectral performance, it is not recommended to use more

than ±8mV adjustment from the default setting

Input Clock Coarse Phase Adjustment

Coarse adjustment is available in register 0x02. The typical range is approximately 73 ps with a resolution of

2.4ps.

Input Clock Fine Phase Adjustment

Fine adjustment is available in register 0x03. The typical range is approximately 7.4 ps with a resolution of 116fs.

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