ADS5400IPZP datasheet(10/48 Pages) TI

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CLKINP

RESETP

Phase 0: CLKOUT indesired

stateafterpowerup

Phase 1: misalignedby 1

clockafterpowerup

tPD-CLKDIV2

CLKOUTAP

CLKOUTBP

DATA BUSB

SYNCOUTB

(OVRBpins)

Sync

SampleNandRESET

pulsecapturedhere

tPD-BDATA

CLKOUT isresetafter 3.5 CLKINcycles (+ tPD-CLKDIV2 )

N+2

N+1

N+3

DATA BUS A

IfSYNCmodeisenabled,

theOVRBpinsbecomeSYNCOUTBpins

LatencyofN+1 is 7.5 CLKINcycles

LatencyofNandSYNCOUTBarematchedto 8.5 CLKINcycles

tPD-ADATA

N+1

ThephaseofdatashownpriortoresetmatchesCLKOUT inphase 0

tRSU

tRH

N, N+1

output

tsu

ADS5400

SLAS611B – OCT 2009 – REVISED MARCH 2010

www.ti.com

Timing Diagrams (continued)

Propagation delays and setup/hold times not drawn to scale. RESET and SYNCOUT are optional. Any clock phase

will work properly, but makes synchronization of data capture across multiple ADCs difficult without a known CLKOUT

phase. RESET can be a single pulse (as shown), low-to-high step or repetitive pulse input signal. The frequency of

repetitive RESET pulses should not exceed CLKIN/2, and should be an even divisor of CLKIN, in order to keep the

CLKOUT phase the same with each RESET event. SYNCOUTB transitions with the same latency as the sample that

is present when the RESET pulse is captured, shown here as sample N. Each RESET captured generates a

SYNCOUT pulse, which behaves as a data bit.

Figure 2. Dual Bus Mode - Aligned, CLKOUT Divide By 2

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