ADS5400IPZP datasheet(31/48 Pages) TI

31 / 48 page

Bipolar

Transistor

Buffer

AINP

AVDD5

AINN

AGND

ADS5400

AGND

Analog

Inputs

Bipolar

Transistor

Buffer

~0.3pF

Package

~0.2pF

Bondpad

~5.25nHBondWire

AVDD5

~0.3pF

Package

~0.2pF

Bondpad

Sampleand

Hold

1 Stage

OfPipeline

~5.25nHBondWire

2.5V

500 W

112 W

0.3pF

500 W

0.3pF

ADS5400

www.ti.com

SLAS611B – OCT 2009 – REVISED MARCH 2010

APPLICATION INFORMATION

Theory of Operation

The ADS5400 is a 12-bit, 1-GSPS, monolithic pipeline ADC. Its bipolar transistor analog core operates from 5-V

and 3.3-V supplies, while the output uses a 3.3-V supply to provide LVDS-compatible digital outputs. The

conversion process is initiated by the falling edge of the external input clock. At the sampling instant, the

differential input signal is captured by the input track-and-hold (T&H), and the input sample is sequentially

converted by a series of lower resolution stages, with the outputs combined in a digital correction logic block.

Both the rising and the falling clock edges are used to propagate the sample through the pipeline every half clock

cycle. This process results in a data latency of 7 - 8.5 clock cycles (output mode dependent), after which the

output data is available as a 12-bit parallel word, coded in offset binary or two's complement format.

The user can select to accept the data at the full sample rate using one bus (bus A, latency 7 cycles), or

demultiplex the data into two buses (bus A and B, latency 7.5 or 8.5 cycles) at half rate. A serial peripheral

interface (SPI) is provided for adjusting operational modes, as well as for calibrations of analog gain, analog

offset and clock phase for inter-leaving multiple ADS5400. Die temperature readout using the SPI is provided.

SYNC and RESET modes exist for synchronizing output data across multiple ADS5400.

Input Configuration

The analog input for the ADS5400 consists of an analog pseudo-differential buffer followed by a bipolar transistor

track-and-hold (see Figure 27). The integrated analog buffer isolates the source driving the input of the ADC from

sampling glitches on the T&H and allows for the integration of a 100-

Ω differential input resistor. The input

common mode is set internally through a 500-

Ω resistor connected from half of the AVDD5 supply voltage to

each of the inputs. The parasitic package capacitance shown is with the package unsoldered. Once soldered,

depending on the board characteristics, one can expect another ~1pF at the analog input pins, which is board

dependent.

Figure 27. Analog Input Equivalent Circuit

For a full-scale differential input, each of the differential lines of the input signal swing symmetrically between 2.5

V + 0.5 V and 2.5 V – 0.5 V. This means that each input has a maximum signal swing of 1 VPP for a total

differential input signal swing of 2 VPP. The maximum fullscale range can be programmed from 1.5-2Vpp using

the SPI. The maximum swing is determined by the internal reference voltage generator and the fullscale range

set using the SPI, eliminating the need for any external circuitry for this purpose. The analog gain adjustment has

a resolution of 12-bits across the 1.5-2VPP range, providing for fine calibration of analog gain mismatches across

multiple ADS5400 signal chains, primarily for interleaving.

Product Folder Link(s): ADS5400

ADS5400IPZP датащи(PDF) 31 Page - Texas Instruments

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