ATmega16U4 datasheet(43/408 Pages) ATMEL

43 / 408 page

7766D–AVR–01/09

ATmega16U4/ATmega32U4

7.1

Idle Mode

When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle

mode, stopping the CPU but allowing the USB, SPI, USART, Analog Comparator, ADC, 2-wire

Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating. This

sleep mode basically halts clk

CPU and clkFLASH, while allowing the other clocks to run.

Idle mode enables the MCU to wake up from external triggered interrupts as well as internal

ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the

Analog Comparator interrupt is not required, the Analog Comparator can be powered down by

setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will

reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automati-

cally when this mode is entered.

7.2

ADC Noise Reduction Mode

When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC

Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, 2-wire

Serial Interface address match and the Watchdog to continue operating (if enabled). This sleep

mode basically halts clkI/O, clkCPU, and clkFLASH, while allowing the other clocks to run

(including clkUSB).

This improves the noise environment for the ADC, enabling higher resolution measurements. If

the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the

ADC Conversion Complete interrupt, only an External Reset, a Watchdog System Reset, a

Watchdog interrupt, a Brown-out Reset, a 2-wire serial interface interrupt, an SPM/EEPROM

ready interrupt, an external level interrupt on INT6, an external interrupt on INT3:0 or a pin

change interrupt can wake up the MCU from ADC Noise Reduction mode.

7.3

Power-down Mode

When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-

down mode. In this mode, the external Oscillator is stopped, while the external interrupts, the 2-

wire Serial Interface, and the Watchdog continue operating (if enabled). Only an External Reset,

a Watchdog Reset, a Brown-out Reset, 2-wire Serial Interface address match, an external level

interrupt on INT6, an external interrupt on INT3:0, a pin change interrupt or an asynchronous

USB interrupt sources (VBUSTI, WAKEUPI), can wake up the MCU. This sleep mode basically

halts all generated clocks, allowing operation of asynchronous modules only.

Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed

level must be held for some time to wake up the MCU. Refer to “External Interrupts” on page 84

for details.

When waking up from Power-down mode, there is a delay from the wake-up condition occurs

until the wake-up becomes effective. This allows the clock to restart and become stable after

having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the

Reset Time-out period, as described in “Clock Sources” on page 28.

7.4

Power-save Mode

When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter Power-

save mode. For compatibility reasons with AT90USB64/128 this mode is still present but since

Timer 2 Asynchronous operation is not present here, this mode is identical to Power-down.

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