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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ATmega16U4 датащи(PDF) 20 Page - ATMEL Corporation |
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ATmega16U4 датащи(HTML) 20 Page - ATMEL Corporation |
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20 / 408 page  20 7766D–AVR–01/09 ATmega16U4/ATmega32U4 The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Z-register. When using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O registers, and the 1.25/2.5Kbytes of internal data SRAM in the ATmega16U4/ATmega32U4 are all accessible through all these addressing modes. The Register File is described in “General Purpose Register File” on page 12. Figure 5-2. Data Memory Map 5.2.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk CPU cycles as described in Figure 5-3. Figure 5-3. On-chip Data SRAM Access Cycles 32 R egisters 64 I/O R egisters I nternal S RAM $0000 - $001F $0020 - $005F $FFFF $0060 - $00FF D ata Memory 160 E xt I/O R eg. ISRAM end : $05FF / $0AFF ISRAM start : $0100 clk WR RD Data Data Address Address valid T1 T2 T3 Compute Address CPU Memory Access Instruction Next Instruction |
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