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ATmega16U4 датащи(PDF) 41 Page - ATMEL Corporation |
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ATmega16U4 датащи(HTML) 41 Page - ATMEL Corporation |
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41 / 408 page ![]() 41 7766D–AVR–01/09 ATmega16U4/ATmega32U4 Figure 6-5. PLL Postcaler operation with division factor = 1.5 • Bit 3..0 – PDIV3:0 PLL Lock Frequency These bits configure the PLL internal VCO clock reference according to the required output fre- quency value. • The optimal PLL configuration at 5V is: PLL output frequency = 96 MHz, divided by 1.5 to generate the 64 MHz High Speed Timer clock, and divided by 2 to generate the 48 MHz USB clock. PDIV3 PDIV2 PDIV1 PDIV0 PLL Output Frequency 0 0 0 0 Not allowed 0 0 0 1 Not allowed 00 1 0 32 MHz 00 1 1 40 MHz 01 0 0 48 MHz 01 0 1 56 MHz 01 1 0 64 MHz 01 1 1 72 MHz 10 0 0 80 MHz 10 0 1 88 MHz 10 1 0 96 MHz 1 0 1 1 Not allowed 1 1 0 0 Not allowed 1 1 0 1 Not allowed 1 1 1 0 Not allowed 1 1 1 1 Not allowed Fi Fi x --- 2 3 |
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