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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ATmega16U4 датащи(PDF) 21 Page - ATMEL Corporation |
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ATmega16U4 датащи(HTML) 21 Page - ATMEL Corporation |
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21 / 408 page  21 7766D–AVR–01/09 ATmega16U4/ATmega32U4 5.3 EEPROM Data Memory The ATmega16U4/ATmega32U4 contains 512Bytes/1K bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Regis- ters, the EEPROM Data Register, and the EEPROM Control Register. For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see page 362, page 367, and page 351 respectively. 5.3.1 EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 5-3. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instruc- tions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 25. for details on how to avoid problems in these situations. In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. 5.3.2 The EEPROM Address Register – EEARH and EEARL • Bits 15..12 – Res: Reserved Bits These bits are reserved bits in the ATmega16U4/ATmega32U4 and will always read as zero. • Bits 11..0 – EEAR8..0: EEPROM Address The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 512Bytes/1K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and E2_END. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. 5.3.3 The EEPROM Data Register – EEDR Bit 151413 1211 10 9 8 –––– EEAR11 EEAR10 EEAR9 EEAR8 EEARH EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL 7654 3 2 1 0 Read/Write RRRR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0000 X X X X XXXX X X X X Bit 7654 32 1 0 MSB LSB EEDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0000 00 0 0 |
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