ATmega16U4 datasheet(37/408 Pages) ATMEL

37 / 408 page

7766D–AVR–01/09

ATmega16U4/ATmega32U4

These bits are reserved and will always read as zero.

• Bit 1 – RCON: RC Oscillator On

This bit is set by hardware to one if the RC Oscillator is running.

This bit is set by hardware to zero if the RC Oscillator is stopped.

• Bit 0 – EXTON: External Clock / Low Power Crystal Oscillator On

This bit is set by hardware to one if the External Clock / Low Power Crystal Oscillator is running.

This bit is set by hardware to zero if the External Clock / Low Power Crystal Oscillator is

stopped.

6.7

Clock Output Buffer

The device can output the system clock on the CLKO pin. To enable the output, the CKOUT

Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other cir-

cuits on the system. The clock also will be output during reset, and the normal operation of I/O

pin will be overridden when the fuse is programmed. Any clock source, including the internal RC

Oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is

used, it is the divided system clock that is output.

6.8

System Clock Prescaler

The AVR USB has a system clock prescaler, and the system clock can be divided by setting the

“Clock Prescaler Register – CLKPR” on page 37. This feature can be used to decrease the sys-

tem clock frequency and the power consumption when the requirement for processing power is

low. This can be used with all clock source options, and it will affect the clock frequency of the

CPU and all synchronous peripherals. clk

I/O, clkADC, clkCPU, and clkFLASH are divided by a factor

as shown in Table 6-10.

When switching between prescaler settings, the System Clock Prescaler ensures that no

glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than

neither the clock frequency corresponding to the previous setting, nor the clock frequency corre-

sponding to the new setting.

The ripple counter that implements the prescaler runs at the frequency of the undivided clock,

which may be faster than the CPU's clock frequency. Hence, it is not possible to determine the

state of the prescaler - even if it were readable, and the exact time it takes to switch from one

clock division to the other cannot be exactly predicted. From the time the CLKPS values are writ-

ten, it takes between T1 + T2 and T1 + 2 * T2 before the new clock frequency is active. In this

interval, 2 active clock edges are produced. Here, T1 is the previous clock period, and T2 is the

period corresponding to the new prescaler setting.

To avoid unintentional changes of clock frequency, a special write procedure must be followed

to change the CLKPS bits:

Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in

CLKPR to zero.

Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.

Interrupts must be disabled when changing prescaler setting to make sure the write procedure is

not interrupted.

6.8.1

Clock Prescaler Register – CLKPR

Bit

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