ATmega16U4 datasheet(28/408 Pages) ATMEL

28 / 408 page

7766D–AVR–01/09

ATmega16U4/ATmega32U4

6.1.4

ADC Clock – clk

ADC

The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks

in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion

results.

6.1.5

PLL Prescaler Clock – clk

PllPresc

The PLL requires a 8 MHz input. A prescaler allows user to use either a 8MHz or a 16MHz

source (from a crystal or an external source), using a divider (by 2) if necessary. The output of

the prescaler goes into the PLL Input multiplexer, that allows the user to select either the pres-

caler output of the System Clock Multiplexer, or the Internal 8MHz Calibrated Oscillator.

6.1.6

PLL Output Clock – clk

Pll

When enabled, the PLL outputs one frequency among numerous choices between 32MHz and

96 MHz. The output frequency is determined by the PLL clock register. The frequency is inde-

pendent of the power supply voltage. The PLL Output is connected to a postcaler that allows

user to generate two different frequencies (clk

USB and clkTMR) from the common PLL signal,

each on them resulting of a selected division ratio (/1, /1.5, /2).

6.1.7

High-Speed Timer Clock– clk

TMR

When enabled, the PLL outputs one frequency among numerous choices between 32MHz and

96 MHz, that goes into the PLL Postcaler. The High Speed Timer frequency input is generated

from the PLL Postcaler, that proposes /1, /1.5 and /2 ratios. That can be determined from the

PLL clock register. The High Speed Timer maximum frequency input depends on the power sup-

ply voltage and reaches its maximum of 64 MHz at 5V.

6.1.8

USB Clock – clk

USB

The USB hardware module needs for a 48 MHz clock. This clock is generated from the on-chip

PLL. The output of the PLL passes through the PLL Postcaler where the frequency can be either

divided by 2 or directly connected to the clk

USB signal.

6.2

Clock Sources

The device has the following clock source options, selectable by Flash Fuse bits as shown

below. The clock from the selected source is input to the AVR clock generator, and routed to the

appropriate modules.

Note:

1. For all fuses “1” means unprogrammed while “0” means programmed.

Table 6-1.

Device Clocking Options Select(1)

Device Clocking Option

CKSEL[3:0]

(or EXCKSEL[3:0])

Low Power Crystal Oscillator

1111 - 1000

Reserved

0111 - 0110

Low Frequency Crystal Oscillator

0101 - 0100

Reserved

0011

Calibrated Internal RC Oscillator

0010

External Clock

0000

Reserved

0001

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