ATmega16U4 datasheet(77/408 Pages) ATMEL

77 / 408 page

7766D–AVR–01/09

ATmega16U4/ATmega32U4

•INT3/TXD1 – Port D, Bit 3

INT3, External Interrupt source 3: The PD3 pin can serve as an external interrupt source to the

MCU.

TXD1, Transmit Data (Data output pin for the USART1). When the USART1 Transmitter is

enabled, this pin is configured as an output regardless of the value of DDD3.

•INT2/RXD1 – Port D, Bit 2

INT2, External Interrupt source 2. The PD2 pin can serve as an External Interrupt source to the

MCU.

RXD1, Receive Data (Data input pin for the USART1). When the USART1 receiver is enabled

this pin is configured as an input regardless of the value of DDD2. When the USART forces this

pin to be an input, the pull-up can still be controlled by the PORTD2 bit.

•INT1/SDA – Port D, Bit 1

INT1, External Interrupt source 1. The PD1 pin can serve as an external interrupt source to the

MCU.

SDA, 2-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to enable the 2-wire

Serial Interface, pin PD1 is disconnected from the port and becomes the Serial Data I/O pin for

the 2-wire Serial Interface. In this mode, there is a spike filter on the pin to suppress spikes

shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with slew-

rate limitation.

•INT0/SCL/OC0B – Port D, Bit 0

INT0, External Interrupt source 0. The PD0 pin can serve as an external interrupt source to the

MCU.

SCL, 2-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) to enable the 2-

wire Serial Interface, pin PD0 is disconnected from the port and becomes the Serial Clock I/O

pin for the 2-wire Serial Interface. In this mode, there is a spike filter on the pin to suppress

spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with

slew-rate limitation.

OC.0B: Timer 0 Output Compare B. This pin can be used to generate a PWM signal from the

Timer 0 module.

Table 10-9 and Table 10-10 relates the alternate functions of Port D to the overriding signals

shown in Figure 10-5 on page 69.

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