7477 datasheet(16/354 Pages) RENESAS

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7470/7471/7477/7478 GROUP USER’S MANUAL

List of figures

Fig. 2.4.9 Example of control procedure [Clock synchronous serial I/O mode, 7477/7478

group] ............................................................................................................................. 2-31

Fig. 2.4.10 Example of connections [Clock asynchronous serial I/O mode, 7477/7478

group] ............................................................................................................................. 2-32

Fig. 2.4.11 Example of control procedure [Clock asynchronous serial I/O mode, 7477

/7478 group] ................................................................................................................ 2-33

Fig. 2.5.1 Memory map of A-D conversion related registers .................................................. 2-35

Fig. 2.5.2 Example of A-D conversion control procedure ....................................................... 2-37

Fig. 2.5.3 Analog input internal equivalent circuit .................................................................... 2-38

Fig. 2.6.1 Example of reset circuit .............................................................................................. 2-39

Fig. 2.7.1 Example of Oscillation circuit using ceramic resonator ......................................... 2-40

Fig. 2.7.2 Example of external clock input circuit .................................................................... 2-40

Fig. 2.8.1 Structure of CPU mode register ................................................................................. 2-41

Fig. 2.8.2 Example of control procedure [Ordinary mode

→ Stop mode → Ordinary mode] ... 2-43

Fig. 2.8.3 Example of control procedure [Ordinary mode

→ Wait mode → Ordinary mode] ... 2-44

Fig. 2.8.4 Example of control procedure [Ordinary mode

→ Low-speed mode] .................. 2-45

Fig. 2.8.5 Example of control procedure [Low-speed mode

→ Ordinary mode] .................. 2-46

__________________________

Fig. 2.9.1 Wiring for the RESET pin ............................................................................................ 2-48

Fig. 2.9.2 Wiring for clock I/O pins ............................................................................................. 2-49

Fig. 2.9.3 Wiring for the VPP pin of the One Time PROM and the EPROM version ......... 2-50

Fig. 2.9.4 Bypass capacitor across the VSS line and the VCC line ....................................... 2-51

Fig. 2.9.5 Analog signal line and a resistor and a capacitor ................................................. 2-51

Fig. 2.9.6 Wiring for a large current signal line ....................................................................... 2-52

Fig. 2.9.7 Wiring to a signal line where potential levels change frequently ........................ 2-52

Fig. 2.9.8 Setup for I/O ports ....................................................................................................... 2-53

Fig. 2.9.9 Watchdog timer by software ....................................................................................... 2-55

Fig. 2.10.1 Initialization of flags in PS ........................................................................................ 2-56

Fig. 2.10.2 Stack memory contents after PHP instruction execution .................................... 2-56

Fig. 2.10.3 Note to execute by PLP instruction ........................................................................ 2-56

Fig. 2.10.4 Note for decimal operation ....................................................................................... 2-57

Fig. 2.12.1 Application circuit example 1 (cleaner) .................................................................. 2-59

CHAPTER 3. APPENDIX

Fig. 3.1.1 Structure of Port Pi direction register (i = 0, 1, 2, 4) ............................................. 3-2

Fig. 3.1.2 Structure of Port P0 pull-up control register ............................................................. 3-2

Fig. 3.1.3 Structure of Ports P1 to P5 pull-up control register ................................................ 3-3

Fig. 3.1.4 Structure of Edge polarity selection register ............................................................. 3-3

Fig. 3.1.5 Structure of Input latch register ................................................................................... 3-4

Fig. 3.1.6 Structure of A-D control register .................................................................................. 3-4

Fig. 3.1.7 Structure of A-D conversion register ........................................................................... 3-5

Fig. 3.1.8 Structure of Serial I/O mode register ..........................................................................3-5

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